Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
Transceiver Loopback Delays
Ordering Information
Core1553BRT-EBR can be ordered through your local
Actel sales representative. It should be ordered using the
following number scheme: Core1553BRT-EBR-XX, where
XX is listed in Table 18.
Core1553BRT-EBR verifies that all transmitted data words
are correctly transmitted. As data is transmitted by the
transceiver on the 1553EBR bus, it is monitored by the
transceiver and decoded by Core1553BRT-EBR. The core
requires that the loopback delay, i.e., the time from
BUSAOUT to BUSAIN, be less than 180 ns.
Table 18 • Ordering Codes
XX
EV
Description
The loopback delay is a function of the internal FPGA
delay, PCB routing delays, internal transceiver delay, and
transmission effects from the 1553EBR bus. Additional
register stages may be inserted on either the 1553EBR
data input or output within the FPGA, providing the
required loopback delay is not violated.
Evaluation version
SN
AN
SR
Netlist for single-use on Actel devices
Netlist for unlimited use on Actel devices
RTL for single-use on Actel devices
AR
UR
RTL for unlimited use on Actel devices
RTL for unlimited use and not restricted to Actel devices
Clock Requirements
To meet 1553EBR transmission bit rate requirements, the
Core1553BRT-EBR clock input must be 100 MHz 0.01%.
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version
Changes in Current Version (Advanced v1.1)
The product name was changed from Core1553EBRRT to Core1553BRT-EBR.
Changed "MIL-STD-1553EBR" to "MIL-STD-1553B" under "Verification and Compliance"
First bullet added under "Verification and Compliance"
Page
N/A
1
Advanced v1.0
1
Changed "SAE AIR5610" to "SAE AS5682" under "RT-to-RT Transfer Support"
Changed Time values in Table 17
14
24
25
Changed maximum loopback delay under "Transceiver Loopback Delays"
Advanced v1.1
25
ACTEL [ Actel Corporation ]
