Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
Specifications
Memory Write Timing – Asynchronous Mode
CLK
ADDRLAT
MEMREQn
MEMGNTn
MEMCEN
MEMDEN
MEMCSn
MEMADDR
MEMOPER
Valid Address
Valid Operation
Valid Data
MEMDATA
MEMWRn
MEMWAITn
Figure 11 • Memory Write Timing – Asynchronous Mode
Memory Write Timing
Table 14 • Memory Write Timing
Sync Mode
TpwWR
Description
Write pulse width (no wait states)
Time
1 clock cycle
1.2 µs
TpdGNT
Maximum delay from MEMREQn to MEMGNTn active
Data setup time to MEMWRn low
TsuDATA
1 clock cycle
1 clock cycle
1 clock cycle
1 clock cycle
1 clock cycle
TsuADDR
ThdDATA
ThdADDR
TsuWAIT
Address setup time to MEMWRn low
Data hold time from MEMWRn high
Address hold time from MEMWRn high
Wait setup to rising clock edge
20
Advanced v1.1
ACTEL [ Actel Corporation ]
