Core1553BBC MIL-STD-1553B Bus Controller
CLK
Timeout
MEMREQn
MEMGNTn
MEMCEN
MEMDEN
MEMCSn
MEMRDn/WRn
Tsu
MEMWAITn
MEMFAIL
Figure 22 • Memory Wait Time-out
Clock Requirements
To meet the 1553B transmission bit rate requirements, the Core1553BBC clock input must be 12, 16, 20, or 24 MHz with
a tolerance of 0.01ꢀ.
Ordering Information
Core1553BBC can be ordered through your local Actel sales representative. It should be ordered using the following
number scheme: Core1553BBC-XX, where XX is (Table 19):
Table 19 • Ordering Codes
XX Description
EV Evaluation Version
SN Netlist for single-use on Actel devices
AN Netlist for unlimited use on Actel devices
SR RTL for single-use on Actel devices
AR RTL for unlimited use on Actel devices
UR RTL for unlimited use and not restricted to Actel devices
The Evaluation board can also be ordered using the order code "Core1553BBC Eval Board."
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v4.0
ACTEL [ Actel Corporation ]
