Core1553BBC MIL-STD-1553B Bus Controller
memory connected to the core and removes the need for
external bus arbitration on the CPU bus.
Typical BC System
Core1553BBC requires a master CPU to set up the data
tables. The CPU needs to be able to access the internal
core registers as well as the backend memory.
Core1553BBC can be configured in two ways with the
CPU shared memory and with its own memory.
Alternatively, the core can share the CPU memory as
shown in Figure 9 on page 23. In this case, both the
backend memory and CPU interfaces are connected to
the CPU bus. The core provides control lines that allow
the memory and CPU interfaces to share the same top-
level I/O pins. When in this configuration, the core needs
to read or write the memory it uses MEMREQn and
MEMGNTn signals to arbitrate for the CPU bus before
completing the cycle.
When configured with its own memory, only the CPU
port needs to be connected to the CPU. The CPU accesses
the
backend
memory
via
Core1553BBC.
This
configuration also supports using an internal FPGA
Pulse
Transformer
BUSAINEN
RCVSTBA
RXDAIN
RXDAIN
BUSAINP
Memory
BUSAINN
BUSAOUTINH
BUSAOUTP
BUSAOUTN
TXINHA
TXDAIN
TXDAIN
Transceiver
Pulse
Transformer
BUSBINEN
BUSBINP
BUSBIN
RCVSTBA
RXDBIN
RXDBIN
CPU
BUSAOUTINH
BUSBOUTP
BUSBOUTN
TXINHA
TXDBIN
TXDBIN
Core1553BBC
Actel FPGA
Figure 8 • Core1553BBC with Its Own Memory
22
v4.0
ACTEL [ Actel Corporation ]
