Core1553BBC MIL-STD-1553B Bus Controller
message gap; this specifies the delay to the next
message. Finally, the WAITC and DELAY instructions can
be used to insert extra delays between messages.
Asynchronous Messages
Core1553BBC supports asynchronous messages. While
idle, or when a normal message list is being processed,
the CPU can initiate the core to jump to a secondary
(asynchronous) message list and process these messages.
When complete, the core will go back to the original
message list.
The actual IMG gap is also a function of the backend
memory access system. There is a six-cycle overhead
required between each message to read and write to the
message block. These six memory accesses directly effect
the inter-message gap. The actual IMG will be the largest
of the duration of these six memory cycles or the
programmed IMG value.
The asynchronous message list can be started directly by
the CPU by writing to the control register. When the
current message completes, the core pushes the current
LISTPTR address on the stack and loads the LISTPTR with
the value specified in the ASYNCPTR. It will execute these
instructions until a RETAS instruction is found. At this
point, the LISTPTR is reloaded from the stack and the bus
controller enters the idle state or resumes the original
instruction list. While the asynchronous message list is
being processed, the START instruction and further
asynchronous events are disabled. They are re-enabled
by the RETAS instruction.
Bus Transceivers
Core1553BBC needs a 1553B transceiver to drive the
1553B bus. Core1553BBC is designed to directly interface
to common MIL-STD-1553 transceivers, such as the DDC
BU-63147 and the Aeroflex ACT4402. When using
ProASICPLUS or Axcelerator, level translators are required
to connect the 5V output levels of the 1553B transceivers
to the 3.3V input levels of the FPGA.
In addition to the transceiver, a pulse transformer is
required for interfacing to the 1553B bus. Figure 7 on
page 21, Figure 8 on page 22, and Figure 9 on page 23
show the connections required from the Core1553BBC to
the transceivers and then to the bus via the pulse
transformers.
Retry Operations
Core1553BBC supports an automatic retry system that
retries messages that fail automatically. On detecting an
error that can be retried, the BC immediately retries the
message. Each message can be retried up to six times.
The Core1553BBC can be programmed to retry up to
three times on the original bus, then retry up to three
times on the alternative bus, or to simply retry initially
on the alternative bus and then switch buses after each
attempt.
Development System
A complete 1553B Bus controller development system is
also available. The Actel part number is “Core1553BBC
Eval Board." The development system implements a PCI
to 1553B bus controller on a single PCB using an Actel
A54SX32A FPGA.
Inter-Message Gap (IMG) Control
Core1553BBC provides several ways to control the 1553B
inter-message gaps. First, a default IMG is programmed
into the Core1533BBC control register. Secondly every
message block can be programmed with its own inter-
The PCI target interface uses the Actel CorePCI66 PCI
target interface core.
20
v4.0
ACTEL [ Actel Corporation ]
