AC Electrical Characteristics † - Clock Timing (Figures 12 and 13)
Characteristics
Sym
Min Typ ‡ Max
Units
ns
Test Conditions
1
2
3
4
5
6
7
Clock Period*
tCLK
220
95
244
122
122
20
300
150
150
Clock Width High
Clock Width Low
t
CH
ns
t
CL
110
ns
Clock Transition Time
Frame Pulse Setup TIme
Frame Pulse Hold Time
Frame Pulse Width
t
CTT
ns
t
CCT
20
ns
t
FPH
0.020
670
µs
ns
t
FPW
244
†† Timing is over recommended temperature & power supply voltages.
‡
*
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high
impedance state. NB: Frame Pulse is repeated every 512 cycles of C4i
.
Figure 12 Frame Allignment
C4i
FOi
Bit
Cells
Channel 31
Bit 0
Channel 0
Bit 7
Figure 13 Clock Timing
t
CLK
t
t
CH
t
CTT
CL
2.0V
0.8V
C4i
F0i
t
t
CTT
CHL
t
t
FPS
FPH
t
t
FPH
FPS
2.0V
0.8V
t
FPW
9
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