V-Data
VDS6632A4A
AC Characteristics
-5
-5.5
Max
-6
Parameter
Symbol
Unit
ns
Note
Min
5
Max
Min
5.5
10
Min
6
Max
System clock
Cycle time
/CAS Latency = 3 tCK3
/CAS Latency = 2 tCK2
1000
1000
1000
10
2
10
2.5
2.5
-
Clock high pulse width
Clock low pulse width
tCHW
tCLW
-
-
2.25
2.25
-
-
-
-
ns
ns
1
1
2
-
Access time form /CAS Latency = 3 tAC3
-
4.5
6
-
5
6
-
5.5
ns
ns
2
clock
/CAS Latency = 2 tAC2
-
-
-
6
Operation
tRC
55
55
15
40
15
10
1
55
60
60
18
42
18
12
1
-
/RAS cycle time
Auto Refresh
tRRC
tRCD
tRAS
tRP
-
55
-
-
/RAS to /CAS delay
-
16.5
-
-
ns
ns
/RAS active time
100K 38.5 100K
100K
/RAS precharge time
/RAS to /RAS bank active delay
/CAS to /CAS delay
-
-
16.5
11
1
-
-
-
-
ns
tRRD
tCCD
tWTL
tDPL
tDAL
tDQZ
tDQM
tOH
ns
-
-
-
CLK
CLK
CLK
CLK
CLK
CLK
ns
Write command to data – in delay
Data – in to precharge command
Data – in active command
DQM to data – out Hi-Z
DQM to data – in mask
Data – out hold time
Data – input setup time
Data – input hold time
Address setup time
0
-
0
-
0
-
1
-
1
-
1
-
5
-
5
-
5
-
2
-
2
-
2
-
0
-
0
-
0
-
1.5
1.5
1
-
2
-
2
-
tDS
-
1.5
1
-
1.5
1
-
ns
1
1
1
1
1
1
1
1
tDH
-
-
-
ns
tAS
1.5
1
-
1.5
1
-
1.5
1
-
ns
Address hold time
tAH
-
-
-
ns
CKE setup time
tCKS
tCKH
tCS
1.5
1
-
1.5
1
-
1.5
1
-
ns
CKE hold time
-
-
-
ns
Command setup time
Command hold time
CLK to data output in low Z-time
MRS to new command
Power down exit time
Self refresh exit time
Refresh time
1.5
1
-
1.5
1
-
1.5
1
-
ns
tCH
-
-
-
ns
tOLZ
tMRD
tPDE
tSRE
tREF
1
-
1
-
1
-
ns
2
-
2
-
2
-
CLK
CLK
CLK
ms
1
-
1
-
1
-
1
-
1
-
1
-
3
-
64
-
64
-
64
Note : 1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
Rev 1.0 April, 2001
6
ADATA [ ADATA Technology Co., Ltd. ]
