V-Data
VDS6632A4A
Pin Description
PIN
NAME
FUNCTION
CLK
CKE
System Clock
Active on the positive edge to sample all inputs.
Clock Enable
Chip Select
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Disables or Enables device operation by masking or enabling all input
except CLK, CKE and DQM0 ~ DQM3
A0~A11 Address
Row / Column address are multiplexed on the same pins.
Row address : RA0~RA10
Column address : CA0~CA7
BA0~BA1 Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Data inputs / outputs are multiplexed on the same pins.
Makes data output Hi-Z,
DQ0~DQ31 Data
DQM0~3 Data Mask
/RAS
/CAS
/WE
Row Address Strobe
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS low
Enables write operation and row recharge.
Column Address Strobe
Write Enable
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers.
NC
No Connection
This pin is recommended to be left No Connection on the device.
Block Diagram
CLK
Clock
Generator
Bank3
Bank2
CKE
Bank1
Address
Address
Buffer
&
Bank0
Mode
Register
Refresh
Counter
Amplifier
DQM
/CS
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
/RAS
/CAS
Data Control Circuit
DQ
/WE
Rev 1.0 April, 2001
2
ADATA [ ADATA Technology Co., Ltd. ]
