ICL7104
t
t
SM
CWH
H
L
CLOCK 1
(PIN 25)
t
MW
H
L
EITHER:
DON’T CARE
STABLE
MODE PIN
OR
INTERNAL
LATCH PULSE IF
MODE “HI”
IGNORED
IGNORED
UART
INTERNAL
MODE
NORM
t
t
CEH
CEL
H
CE/LD
L
t
t
ME
CEZ
t
EXT
EXT
SS
SEN
H
DON’T CARE
DON’T CARE
(EXTERNAL
SIGNAL)
L
t
MB
H
L
HBEN
t
t
t
CBZ
CBL
CBH
H
L
O/R, POL
01-14
DATA VALID, STABLE
t
t
CDL
CDH
H
L
LBEN
DATA VALID, STABLE
BITS 1-5
HANDSHAKE MODE
TRIGGERED BY
THREE-STATE
-16 HAS EXTRA (MBEN) PHASE
OR
THREE-STATE WITH PULLUP
FIGURE 5. HANDSHAKE MODE TIMING DIAGRAM
Detailed Description
ANALOG SECTION
unbalanced condition exists compared to the Auto-Zero
phase, and the integrator will generate a ramp whose slope
Figure 6 shows the equivalent Circuit of the Analog Section
of both the ICL7104/8052 and the ICL7104/8068 in the 3
different phases of operation. If the Run/Hold pin is left open
or tied to V+, the system will perform conversions at a rate
determined by the clock frequency: 131,072 for - 16 and
32,368 for - 14 clock periods per cycle (see Figure 8
conversion timing).
is proportional to V . At the end of this phase, the sign of
IN
the ramp is latched into the polarity F/F.
Deintegrate Phase III (Figures 6C and 6D)
During the Deintegrate phase, the switch drive logic uses the
output of the polarity F/F in determining whether to close
switches 6 and 9 or 7 and 8. If the input signal was positive,
Auto-Zero Phase I (Figure 6A)
switches 7 and 8 are closed and a voltage which is V
REF
more negative than during Auto-Zero is impressed on the
buffer input. Negative inputs will cause +V to be applied
During Auto-Zero, the input of the buffer is shorted to analog
ground thru switch 2, and switch 1 closes a loop around the
integrator and comparator. The purpose of the loop is to
charge the Auto-Zero capacitor until the integrator output no
longer changes with time. Also, switches 4 and 9 recharge
REF
to the buffer input via switches 6 and 9. Thus, the reference
capacitor generates the equivalent of a (+) reference or a (-)
reference from the single reference voltage with negligible
error. The reference voltage returns the output of the inte-
grator to the zero-crossing point established in Phase I. The
time, or number of counts, required to do this is proportional
to the input voltage. Since the Deintegrate phase can be
twice as long as the Input integrate phase, the input voltage
the reference capacitor to V
.
REF
Input Integrate Phase II (Figure 6B)
During input integrate the Auto-Zero loop is opened and the
analog input is connected to the buffer input thru switch 3.
(The reference capacitor is still being charged to V
required to give a full scale reading = 2V
.
REF
REF
during this time.) If the input signal is zero, the buffer,
integrator and comparator will see the same voltage that
existed in the previous sate (Auto-Zero). Thus the integrator
output will not change but will remain stationary during the
NOTE: Once a zero crossing is detected, the system automatically
reverts to Auto-Zero phase for the leftover Deintegrate time (unless
RUN/HOLD is manipulated, see RUN/HOLD input in detailed
description, digital section).
entire Input Integrate cycle. If V is not equal to zero, an
IN
8
ETC [ ETC ]
