ICL7104
t
CEA
CE/LD
AS INPUT
t
BEA
HBEN
AS INPUT
MBEN
AS INPUT
LBEN
AS INPUT
t
t
DHB
DAB
HIGH BYTE
DATA
DATA
DATA
VALID
VALID
t
t
DHC
DAC
MIDDLE
BYTE
ENABLE
DATA
VALID
DATA
VALID
LOW BYTE
ENABLE
DATA
VALID
= HIGH IMPEDANCE
FIGURE 4. DIRECT MODE TIMING DIAGRAM
TABLE 1. DIRECT MODE TIMING REQUIREMENTS (Note: Not tested in production)
SYMBOL
DESCRIPTION
MIN
TYP
300
300
200
350
350
280
1000
MAX
UNIT
ns
t
t
XBEN (Min) Pulse Width.
Data Access Time from XBEN.
Data Hold Time from XBEN.
CE/LD Min. Pulse Width.
Data Access Time from CE/LD.
Data Hold Time from CE/LD.
CLOCK 1 High Time.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BEA
DAB
DHB
ns
t
ns
t
ns
CEA
DAC
DHC
t
ns
t
ns
t
ns
CWH
TABLE 2. HANDSHAKE TIMING REQUIREMENTS (Note: Not tested in production)
SYMBOL
DESCRIPTION
MIN
TYP
20
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Mode Pulse (Min).
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MW
t
Mode Pin Set-Up Time.
-
-150
200
SM
ME
MB
t
Mode Pin High to Low Z CE/LD High Delay.
Mode Pin High to XBEN Low Z (High) Delay.
Clock 1 High to CE/LD Low Delay.
Clock 1 High to CE/LD High Delay.
Clock 1 High to XBEN Low Delay.
Clock 1 High to XBEN High Delay.
Clock 1 High to Data Enabled Delay.
Clock 1 Low to Data Disabled Delay.
Send ENABLE Set-Up Time.
-
t
-
200
t
-
700
CEL
t
-
600
CEH
t
-
900
CBL
CBH
CDH
t
-
700
t
-
1100
1100
-350
2000
2000
1000
t
-
CDL
t
-
SS
t
t
Clock 1 High to XBEN Disabled Delay.
Clock 1 High to CE/LD Disabled Delay.
Clock 1 High Time.
-
-
CBZ
CEZ
t
1250
CWH
7
ETC [ ETC ]
