ICL7104
R
C
INT
INT
-AN
I/P
BUFFER
INTEGRATOR
COMP.
3
8
-
-
ZERO
CROSS.
DET.
A1
+
A2
+
-
D
Q
A3
+
ZERO
CROSSING
F/F
2
6
7
C
AZ
CL
9
1
CL
POL
-
C
+
V
REF
4
REF
FIGURE 6D. PHASE III DEINTEGRATE
TABLE 3. THREE-STATE BYTE FORMATS AND ENABLE PINS
CE/LD
HBEN
MBEN
LBEN
B5 B4
LBEN
ICL7104-16 POL O/R B16 B15 B14 B13 B12 B11 B10
B9
B9
B8
B8
B7
B7
B6
B6
B3
B3
B2
B2
B1
B1
HBEN
ICL7104-14
POL O/R B14 B13 B12 B11 B10
B5
B4
TABLE 4. TYPICAL COMPONENT VALUES (V++ = +15V, V+ = 5V, V- = 5V, V- = -15V, f
= 200kHz)
CLOCK
ICL8052/8068 WITH
Full scale V
ICL7104-16
ICL7104-14
UNIT
200
10
800
1
4000
1
100
10
47
0.1
1
4000
1
mV
V/V
kΩ
µF
IN
Buffer Gain
R
C
C
C
100
0.33
1
43
0.33
1
200
0.33
1
180
0.1
1
INT
INT
AZ
µF
10
1
1
10
50
6.1
1
µF
REF
REF
V
100
3.1
400
12
2000
61
2000
244
mV
µV
Resolution
Buffer Gain
ICL8052 vs ICL8068
At the end of the auto-zero interval, the instantaneous noise The ICL8052 offers significantly lower input leakage currents
voltage on the auto-zero capacitor is stored, and subtracts from than the ICL8068, and may be found preferable in systems
the input voltage while adding to the reference voltage during with high input impedances. However, the ICL8068 has
the next cycle. The result is that this noise voltage effectively is substantially lower noise voltage, and for systems where
somewhat greater than the input noise voltage of the buffer system noise is a limiting factor, particularly in low signal
itself during integration. By introducing some voltage gain into level conditions, will give better performance.
the buffer, the effect of the auto-zero noise (referred to the
input) can be reduced to the level of the inherent buffer noise.
This generally occurs with a buffer gain of between 3 and 10.
Component Value Selection
For optimum performance of the analog section, care must
be taken in the selection of values for the integrator capaci-
tor and resistor, auto-zero capacitor, reference voltage, and
conversion rate. These values must be chosen to suit the
particular application.
Further increase in buffer gain merely increases the total offset
to be handled by the auto-zero loop, and reduces the available
buffer and integrator swings, without improving the noise per-
formance of the system. The circuit recommended for doing
this with the ICL8068/ICL7104 is shown in Figure 7. With care-
ful layout, the circuit shown can achieve effective input noise
voltages on the order of 1 to 2µV, allowing full 16-bit use with
full scale inputs of a low as 150mV. Note that at this level, ther-
moelectric EMFs between PC boards, IC pins, etc., due to local
temperature changes can be very troublesome. For further dis-
cussion, see Application Note AN030.
10
ETC [ ETC ]
