Ver 1.3
PRELIMINARY
EAGLE
3.27.5 ACK SIGNAL TRANSMISSION
Receiver must send an ACK bit to transmitter to terminate the one byte transfer completely. ACK pulse should be generated
at the 9th SCL clock. One byte transfer consumes 8 clock cycles. Master has to generate the clock pulse for ACK bit.
When transmitter receives an ACK pulse, SDA line is released and the SDA line goes high. On the other side, the receiver
shall keep the SDA line low during the 9th interval of SCL high level which corresponds to the ACK pulse interval,
User may program the TXAK bit of Control register to select the ACK bit as ACK or NOACK.
Clock to Output
Data Output by
Transmitter
Data Output by
Receiver
SCL from
Master
7
1
2
9
8
Start
Start
Condition
Clock Pulse for
Acknowledgement
Figure 3-48 Ack Signal Transmission
3.27.6 READ-WRITE OPERATION
In transmit mode, TWI bus interface must wait until the next data is ready at data shifter register. SCL line is kept low to
load next data on data shifter register. After new data loaded completely, SCL line is released.
During data reception in receive mode, TWI bus interface should keep the SCL line low until data is read. After the new
data is read, SCL is released to allow the reception of next data at shifter register.
3.27.7 BUS ARBITRATION PROCEDURES
This prevents several masters from controlling the bus at the same time. If a master driving the SDA line level to high detects
another master is driving the SDA line to low, this master does not transmit data because it has lost the control of bus.
(1) If device 1 and device 2 are both operating in master mode, both devices shall observe the SCL line to achieve
synchronization.
start counting
HIGH period
wait state
CLK1
CLK2
SCL
counter reset
Figure 3-49 Bus Arbitration procedures 1
195
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
