EAGLE
PRELIMINARY
Ver 1.3
3.25
GPIO
3.25.1 Features
1. GPIO register consists of port A to port D.
2. Supports 90 pins. ( Port A[20:6], A[2:0], B[31:28], B[26:21], B[18:13], B[10:5], C[31:0], D[19:10], D[7:0] )
3. Port Direction register sets the I/O Direction
4. Port Direction Mode register configures the I/O direction in bit unit.
5. Port Output Data Level register confirms the current output level.
6. Each port can be configured as High or Low in bit unit by configuring the Port Output Data Level Setting
Register.
7. Port Input Data Level register confirms the current input level.
3.25.2 Register Map
3.25.2.1 Port Direction Register (PxDIR)
This register indicates the direction of Port A ~ D. This is a read-only register.
Address: FFE0 A400h / FFE0 A420h / FFE0 A440h / FFE0 A460h
Bit
R/W
Description
Default Value
31 : 0
R
Port x Direction bit
0 : Input
0h
1 : Output
3.25.2.2 Port Direction Output Mode Register (PxOUT)
This register sets the output direction for Port A to Port D.
Address: FFE0 A400h / FFE0 A420h / FFE0 A440h / FFE0 A460h
Bit
31 : 0
R/W
W
Description
Port x Direction Output Mode bit
Default Value
-
0 : No effect
1 : Set to output mode the corresponding bit the PxDIR registers
3.25.2.3 Port Direction Input Mode Register (PxIN)
This register sets the input direction for Port A to Port D.
Address: FFE0 A404h / FFE0 A424h / FFE0 A444h / FFE0 A464h
Bit
R/W
Description
Default Value
31 : 0
W
Port x Direction Input Mode bit
0 : No effect
-
1 : Set to input mode the corresponding bit the PxDIR registers
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
188
ETC [ ETC ]
