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NC7SZ373P6 参数 Datasheet PDF下载

NC7SZ373P6图片预览
型号: NC7SZ373P6
PDF下载: 下载PDF文件 查看货源
内容描述: 1位D类锁存器\n [1-Bit D-Type Latch ]
分类和应用: 锁存器逻辑集成电路光电二极管驱动
文件页数/大小: 7 页 / 80 K
品牌: ETC [ ETC ]
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NC7SZ373 TinyLogic UHS D-Type Latch with 3-STATE Output
June 1998
Revised January 2001
NC7SZ373
TinyLogic
UHS D-Type Latch with 3-STATE Output
General Description
The NC7SZ373 is a single positive edge-triggered D-type
CMOS Latch with 3-STATE output from Fairchild’s Ultra
High Speed Series of TinyLogic
in the space saving
SC70 6-lead package. The device is fabricated with
advanced CMOS technology to achieve ultra high speed
with high output drive while maintaining low static power
dissipation over a very broad V
CC
operating range. The
device is specified to operate over the 1.65V to 5.5V range.
The inputs and output are high impedance when V
CC
is 0V.
Inputs tolerate voltages up to 7V independent of V
CC
oper-
ating voltage. The latch appears transparent to the data
when Latch Enable (LE) is HIGH. When LE is LOW, the
data that meets the setup time is latched. The output toler-
ates voltages above V
CC
in the 3-STATE condition.
Features
s
Space saving SC70 6-lead package
s
Ultra High Speed; t
PD
2.6 ns Typ into 50 pF at 5V V
CC
s
High Output Drive;
±
24 mA at 3V V
CC
s
Broad V
CC
Operating Range; 1.65V to 5.5V
s
Matches the performance of LCX when operated at
3.3V V
CC
s
Power down high impedance inputs/output
s
Overvoltage tolerant inputs facilitate 5V to 3V translation
s
Patented noise/EMI reduction circuitry implemented
Ordering Code:
Order
Number
NC7SZ373P6
NC7SZ373P6X
Package
Number
MAA06A
MAA06A
Product Code
Top Mark
Z73
Z73
Package Description
6-Lead SC70, EIAJ SC88, 1.25mm Wide
6-Lead SC70, EIAJ SC88, 1.25mm Wide
Supplied As
250 Units on Tape and Reel
3k Units on Tape and Reel
Pin Descriptions
Pin Names
D
LE
OE
Q
Description
Data Input
Latch Enable Input
Output Enable Input
Latch Output
Logic Symbol
IEEE/IEC
Connection Diagrams
Output
Function Table
Inputs
LE
H
H
L
X
D
L
H
X
X
OE
L
L
L
H
Q
L
H
Q
n-1
Z
(Top View)
Pin One Orientation Diagram
H
=
HIGH Logic Level
X
=
Immaterial
L
=
LOW Logic Level
Z
=
HIGH Impedance
Q
n-1
=
Previous state prior to HIGH-to-LOW transition of latch enable
AAA
=
Product Code Top Mark - see ordering code
Note:
Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin.(see diagram).
TinyLogic is a trademark of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation
DS500157
www.fairchildsemi.com