MAX 3000A Programmable Logic Device Family Data Sheet
Table 2. MAX 3000A Speed Grades
Device
-4
EPM3032A
EPM3064A
EPM3128A
EPM3256A
Note:
(1)
Contact Altera for up-to-date information on the availability of this speed grade.
Speed Grade
-5
-6
-7
v
v
v
v
(1)
v
v
-10
v
v
v
v
v
v
The MAX 3000A architecture supports 100% transistor-to-transistor logic
(TTL) emulation and high-density small-scale integration (SSI),
medium-scale integration (MSI), and large-scale integration (LSI) logic
functions. The MAX 3000A architecture easily integrates multiple devices
ranging from PALs, GALs, and 22V10s to MACH, and pLSI devices.
MAX 3000A devices are available in a wide range of packages, including
PLCC, PQFP, and TQFP packages. See
Table 3.
Table 3. MAX 3000A Maximum User I/O Pins
Device
EPM3032A
EPM3064A
EPM3128A
EPM3256A
Notes:
(1)
(2)
Contact Altera for up-to-date information on available device package options.
When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or
boundary-scan testing, four I/O pins become JTAG pins.
Notes (1), (2)
144-Pin
TQFP
208-Pin
PQFP
44-Pin
PLCC
34
34
44-Pin
TQFP
34
34
100-Pin
TQFP
66
80
96
116
158
MAX 3000A devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 3000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debug cycles, and can be programmed
and erased up to 100 times.
Altera Corporation
3
ETC [ ETC ]
