80C186XL/80C188XL
AC SPECIFICATIONS (Continued)
272431–12
NOTES:
1. Status inactive in state preceding T .
4
2. The data hold time lasts only until INTA goes inactive, even if the INTA transition occurs prior to T
3. INTA occurs one clock later in Slave Mode.
4. For write cycle followed by interrupt acknowledge cycle.
(min).
CLDX
5. LOCK is active upon T of the first interrupt acknowledge cycle and inactive upon T of the second interrupt acknowl-
2
1
edge cycle.
6. Changes in T-state preceding next bus cycle if followed by write.
Pin names in parentheses apply to the 80C188XL.
Figure 8. Interrupt Acknowledge Cycle Waveforms
34
ETC [ ETC ]
