VLSI
Solution
y
DATASHEET
VS1001
K
3. PACKAGES AND PIN DESCRIPTIONS
3.3
LQFP-48
48
1
Figure 3: Pin Configuration, LQFP-48.
Pin Name
nc
XRESET
DGND0
nc
DVDD0
nc
DREQ
DCLK
SDATA
nc
BSYNC
DVDD1
nc
DGND1
XTALO
XTALI
DVDD2
DGND2
DGND3
DGND4
XCS
nc
SCLK
SI
SO
nc
TEST0
TEST1
TEST2
nc
AGND0
AVDD0
RIGHT
AGND1
GBGND
GBUF
GBVDD
RCAP
AVDD1
LEFT
AGND2
nc
Pin
1,2
3
4
5
6
7
8
9
10
11,12
13
14
15
16
17
18
19
20
21
22
23
24. . . 27
28
29
30
31
32
33
34
35,36
37
38
39
40
41
42
43
44
45
46
47
48
Pin Type
-
DI
PWR
-
PWR
-
DO
DI
DI
-
DI
PWR
-
PWR
AO
AI
PWR
PWR
PWR
PWR
DI
-
DI
DI
DO3
-
DI
DO
DO
-
PWR
PWR
AO
PWR
PWR
AO
PWR
AIO
PWR
AO
PWR
-
Function
active low asynchronous reset
digital ground
digital power supply
data request, input bus
serial input data bus clock
serial data input
byte synchronization signal
digital power supply
digital ground
crystal output
crystal input
digital power supply
digital ground
digital ground
digital ground
chip select input (active low)
clock for serial bus
serial input
serial output
reserved for test, connect to DVDD
reserved for test,
do not connect!
reserved for test,
do not connect!
analog ground, low-noise reference
analog power supply
right channel output
analog ground
analog ground
ground buffer
analog power supply
filtering capacitance for reference
analog power supply
left channel output
analog ground
For “Pin Types”, see Chapter 3.1. LQFP-48 package dimensions are at
http://www.vlsi.fi/vs1001/lqfp48.pdf
.
Version 4.14, 2004-02-10
13
ETC [ ETC ]
