DS18B20X
the shift register will contain all 0s. Additional information about the Dallas 1-wire cyclic redundancy
check is available in Application Note 27 entitled “Understanding and Using Cyclic Redundancy Checks
with Dallas Semiconductor Touch Memory Products.”
CRC GENERATOR
Figure 9
XOR
(MSB)
XOR
(LSB)
INPUT
XOR
1-WIRE BUS SYSTEM
The 1-wire bus system uses a single bus master to control one or more slave devices. The DS18B20X is
always a slave. When there is only one slave on the bus, the system is referred to as a “single-drop”
system; the system is “multi-drop” if there are multiple slaves on the bus.
All data and commands are transmitted least significant bit first over the 1-wire bus.
The following discussion of the 1-wire bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-wire signaling (signal types and timing).
HARDWARE CONFIGURATION
The 1-wire bus has by definition only a single data line. Each device (master or slave) interfaces to the
data line via an open drain or 3–state port. This allows each device to “release” the data line when the
device is not transmitting data so the bus is available for use by another device. The 1-wire port of the
DS18B20X (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 10.
The 1-wire bus requires an external pullup resistor of approximately 5 kΩ; thus, the idle state for the 1-
wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle
state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-wire
bus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480
µs,
all components on the bus will be reset.
HARDWARE CONFIGURATION
Figure=NM=
V
PU
DS18B20X 1-WIRE PORT
4.7K
R
X
1-wire Bus
DQ
Pin
R
X
5 µA
Typ.
T
X
R
X
= RECEIVE
T
X
= TRANSMIT
T
X
100
Ω
MOSFET
8 of 21
ETC [ ETC ]
