CY545 Stepper System Controller
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Operating Several CY545s Using a Common Data Bus
In systems where multiple CY545s are to be controlled by a host computer it is possible to use
one eight-bit port to establish a common data bus for sending instructions to the CY545s. Each
of the separate BUSY lines (pin 15 of each CY545 must be monitored individually and each
IO_REQUEST line (pin 13) must be activated separately. This technique effectively uses the
IO_REQUEST line as a chip select (CS). A CY545 will ignore all bus information if its
IO_REQUEST line is inactive.
Synchronization of Two CY545s
Two CY545s, executing similar programs from external
memory, may be synchronized as shown in the figures.
The master CY545 can control a USERBIT line of the
slave CY545 via the Bit command, to set or clear a user
bit. The slave CY545 is started first, with an Execute
command, and executes a Wait command and waits until
the USERBIT line is driven low by the Bit command
executed by the master CY545, when it receives the
(second) Execute command. Both CY545s then proceed
to the next instruction and are synchronized as shown in the timing diagram, to within several
tens of microseconds.
Note that when the
two programs are
not identical, the
master can also use
a Wait command,
while the slave
executes its own Bit
instruction, to
achieve a more
general
synchronization.
© 2002 Cybernetic Micro Systems
93
Chapter 19 - Circuits and Examples
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