CY545 Stepper System Controller
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The CY545 optionally implements a third serial control signal, the CTS signal. You must issue a
Mode command to the CY545 to enable this signal, which shares functions on USRB6. With this
signal enabled, the CY545 indicates to the host system when it is ready for more serial data.
The CTS signal will be turned off when the CY545 is busy executing a command. For long
duration commands, such as time delays or motions, this will inhibit the host from sending more
commands until the CY545 is ready for them, providing an automatic serial handshake.
The CY545 has a three character serial buffer, which should be enough to let the host system
respond to the CTS signal. Otherwise it does not buffer serial received data. The CY545 can
accept serial data continuously within the range of the standard baud rates, until the end of a
command is received (carriage return in ASCII mode). It will then be busy processing the
command, and may take some time, if the command involves a motion, time delay, wait for
external signal, etc. During this time, the CY545 cannot accept any more serial data, and none
should be sent by the host. If the CTS signal has been enabled, this signal will indicate that no
more data should be sent. Otherwise, the host must perform a time delay, allowing the CY545
to execute the current command, before sending more command characters.
When a query command is received, and the CY545 mode register is set to respond out the
serial port (Mode bit MB0 = 0), the query response will be sent on the TxD signal after the
command is received. Note it is possible to issue the query command on the parallel interface,
and have the response sent out the serial side. A typical serial query and response are shown
below.
External Memory Control Signals
As discussed previously, the CY545 can support up to 64K bytes of external data memory, used
for storing and executing various command sequences.
The CY545 provides all address and strobe timing signals to the memory. Signals required are
XMEM_SEL, ALE, WR, RD, and the data bus lines. Special use is made of the data bus, which
provides all 16 bits of address, plus the actual data transfers. Two external latches are required
to hold the address. The example shown uses 74LS373s for this purpose.
When the CY545 reads or writes the external memory, it starts by placing the most significant
address byte on the data bus. It then selects the memory by driving XMEM_SEL low. This both
chip-enables the memory and latches the upper address byte into the 74LS373 which holds
address lines A8 to A15. The CY545 then performs a read or write operation.
© 2002 Cybernetic Micro Systems
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Chapter 16 - Timing and Control
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