PIN CONFIGURATION
Top View
SSOP
PIN DESCRIPTIONS
PIN
1
NAME
DGND
CH B1+
CH B1–
CH B0+
CH B0–
CH A1+
CH A1–
CH A0+
CH A0–
REF
IN
REF
OUT
AGND
+V
A
DESCRIPTION
Digital Ground. Connect directly to analog ground (pin 12).
Non-Inverting Input Channel B1
Inverting Input Channel B1
Non-Inverting Input Channel B0
Inverting Input Channel B0
Non-Inverting Input Channel A1
Inverting Input Channel A1
Non-Inverting Input Channel A0
Inverting Input Channel A0
Reference Input
2.5V Reference Output
Analog Ground. Connect directly to digital ground (pin 1).
Analog Power Supply, +5VDC. Connect directly to digital
power supply (pin 24). Decouple to analog ground with a
0.1µF ceramic capacitor and a 10µF tantalum capacitor.
Selects between the Serial Outputs. When M1 is LOW,
both Serial Output A and Serial Output B are selected for
data transfer. When M1 is HIGH, Serial output A is
configured for both Channel A data and Channel B data;
Serial Output B goes into tri-state (i.e., high impedance).
Selects between two-channel and four-channel opera-
tion. When M0 is LOW, two-channel operation is se-
lected and operates in conjunction with A0. When A0 is
HIGH, Channel A1 and Channel B1 are being con-
verted. When A0 is LOW, Channel A0 and Channel B0
are being converted. When M0 is HIGH, four-channel
operation is selected. In this mode, all four channels are
converted in sequence starting with Channels A0 and
B0, followed by Channels A1 and B1.
A0 operates in conjunction with M0. With M0 LOW and
A0 HIGH, Channel A1 and Channel B1 are converted.
With M0 LOW and A0 LOW, Channel A0 and Channel
B0 are converted.
Convert Start. When CONVST switches from LOW to
HIGH, the device switches from the sample to hold
mode, independent of the status of the external clock.
Synchronization Pulse for the Serial Output.
Chip Select. When LOW, the Serial Output A and Serial
Output B outputs are active; when HIGH, the serial
outputs are tri-stated.
An external CMOS-compatible clock can be applied to
the CLOCK input to synchronize the conversion process
to an external source. The CLOCK pin controls the
sampling rate by the equation: CLOCK = 16 • f
SAMPLE
.
BUSY goes HIGH during a conversion and returns LOW
after the third LSB has been transmitted on either the
Serial A or Serial B output pin.
The Serial Output data word is comprised of channel
information and 12 bits of data. In operation, data is valid
on the falling edge of DCLOCK for 16 edges after the
trailing edge of the RD.
The Serial Output data word is comprised of channel
information and 12 bits of data. In operation, data is valid
on the falling edge of DCLOCK for 16 edges after the
trailing edge of the RD. When M1 is HIGH, both Channel
A data and Channel B data are available.
Digital Power Supply, +5VDC. Connect directly to pin
13. Must be
≤
+V
A
.
ADS7861
1
2
3
4
5
6
7
8
9
DGND
CH B1+
CH B1–
CH B0+
CH B0–
CH A1+
CH A1–
CH A0+
CH A0–
+V
D
24
SERIAL DATA A 23
SERIAL DATA B 22
BUSY 21
CLOCK 20
CS 19
RD 18
CONVST 17
A0 16
M0 15
M1 14
+V
A
13
2
3
4
5
6
7
8
9
10
11
12
13
10 REF
IN
11 REF
OUT
12 AGND
14
M1
15
M0
ABSOLUTE MAXIMUM RATINGS
Analog Inputs to AGND, Any Channel Input ........ –0.3V to (+V
D
+ 0.3V)
REF
IN
..................................................................... –0.3V to (+V
D
+ 0.3V)
Digital Inputs to DGND .......................................... –0.3V to (+V
D
+ 0.3V)
Ground Voltage Differences: AGND, DGND ...................................
±0.3V
+V
D
to AGND ......................... –0.3V to +6V
Power Dissipation .......................................................................... 325mW
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................ –40°C to +85°C
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
16
A0
17
CONVST
18
19
RD
CS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published specifi-
cations.
20
CLOCK
21
BUSY
22
SERIAL
DATA
B
SERIAL
DATA
A
23
24
+V
D
®
3
ADS7861
ETC [ ETC ]
