VLSI
Solution
y
DATASHEET
VS1001
K
3. PACKAGES AND PIN DESCRIPTIONS
3.2
BGA-49
A1 BALL PAD CORNER
1
2
3
4
5
6
7
A
B
4.80
7.00
C
D
E
F
G
0.80 TYP
0.80 TYP
4.80
7.00
1.10 REF
TOP VIEW
Figure 2: Pin Configuration, BGA-49.
Pin Name
BSYNC
DVDD1
DGND1
XTAL0
XTALI
DVDD2
DGND2
XCS
SCLK
SI
SO
TEST0
TEST1
TEST2
AGND1
AVDD1
RIGHT
AGND34
GBGND
GBUF
GBVDD
RCAP
AVDD45
LEFT
AGND56
XRESET
DGND3
DVDD3
DREQ
DCLK
SDATA
Ball
E3
F3
F4
G3
E4
F5
F6
G6
D6
E7
D5
C6
C7
B6
C5
B5
A6
B4
A5
C4
A4
B3
A3
B2
A2
B1
D2
D3
E2
E1
F2
Pin Type
DI
PWR
PWR
CLK
CLK
PWR
PWR
DI
DI
DI
DO3
DI
DO
DO
PWR
PWR
AO
PWR
PWR
AO
PWR
AIO
PWR
AO
PWR
DI
PWR
PWR
DO
DIO
DI
Function
byte synchronization signal
digital power supply
digital ground
crystal output
crystal input
digital power supply
digital ground
chip select input (active low)
clock for serial bus
serial input
serial output
reserved for test, connect to DVDD
reserved for test,
do not connect!
reserved for test,
do not connect!
analog ground
analog power supply
right channel output
analog ground
analog ground for ground buffer
ground buffer
analog power supply for ground buffer
filtering capacitance for reference
analog power supply
left channel output
analog ground
active low asynchronous reset
digital ground
digital power supply
data request, input bus
serial input data bus clock
serial data input
Not connected are: A1, A7, B7, C1, C2, C3, D1, D4, D7, E5, E6, F1, F7, G1, G2, G4, G5 and G7. For
“Pin Types”, see Chapter 3.1. BGA-49 package dimensions are at
http://www.vlsi.fi/vs1001/bga49.pdf
.
1.10 REF
Version 4.14, 2004-02-10
12
ETC [ ETC ]
