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VS1001K 参数 Datasheet PDF下载

VS1001K图片预览
型号: VS1001K
PDF下载: 下载PDF文件 查看货源
内容描述: MPEG音频编解码器 [MPEG AUDIO CODEC]
分类和应用: 解码器编解码器
文件页数/大小: 40 页 / 449 K
品牌: ETC [ ETC ]
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DATASHEET
VS1001
K
VS1001k - MPEG AUDIO CODEC
Features
MPEG audio layer 3 decoder (ISO11172-3)
Supports MPEG 1 & 2, and 2.5 extensions,
all their sample rates and bit rates, in mono
and stereo
Supports PCM input
Supports VBR (variable bitrate)
Can be used as a slave co-processor
Operates with single clock 12..13 MHz or
24..26 MHz
Low-power operation
On-chip high-quality stereo DAC with no
phase error between channels
Internal Op-Amp in BGA-49 and LQFP-48
packages
Stereo earphone driver capable of driving a
30Ω load.
Separate 2.5 .. 3.6V operating voltages for
analog and digital
4 KiB On-chip RAM for user code
Serial control and data interfaces
New functions may be added with software
Description
VS1001k is a single-chip solution for an MPEG
layer 3 audio decoder. The chip contains a high-
performance low-power DSP processor (VS DSP),
working memory, 4 KiB program RAM and 0.5
KiB data RAM for user applications, serial con-
trol and input data interfaces, and a high-quality
oversampling variable-sample-rate stereo DAC, fol-
lowed by an earphone amplifier and a ground buffer.
VS1001k receives its input bitstream through a
serial input bus, which it listens to as a system
slave. The input stream is decoded and passed
through a analog/digital hybrid volume control to
an 18-bit oversampling multi-bit sigma-delta DAC.
The decoding is controlled via a serial control bus.
In addition to the basic decoding, it is possible to
add application specific features, like DSP effects,
to the user RAM memory.
VS1001
stereo
DAC
DREQ
DCLK
SDATA
BSYNC
SO
SI
SCLK
XCS
audio
stereo ear−
phone driver
L
R
output
serial
data
interface
serial
control
interface
SDI
Bus
x−ROM
X Bus
VS_DSP
SCI
Bus
Y Bus
I Bus
x−RAM
y−RAM
y−ROM
program
RAM
program
ROM
Version 4.14, 2004-02-10
1