ST90158 - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
9.1.3.3 Preventing Watchdog System Reset
9.1.3.4 Non-Stop Operation
In order to prevent a system reset, the sequence
AAh, 55h must be written to WDTLR (Watchdog
Timer Low Register). Once 55h has been written,
the Timer reloads the constant and counting re-
starts from the preset value.
In Watchdog Mode, a Haltinstruction is regarded
as illegal. Execution of the Haltinstruction stops
further execution by the CPU and interrupt ac-
knowledgment, but does not stop INTCLK, CPU-
CLK or the Watchdog Timer, which will cause a
System Reset when the End of Count condition is
reached. Furthermore, ST_SP, S_C and the Input
Mode selection bits are ignored. Hence, regard-
less of their status, the counter always runs in
Continuous Mode, driven by the internal clock.
To reload the counter, the two writing operations
must be performed sequentially without inserting
other instructions that modify the value of the
WDTLR register between the writing operations.
The maximum allowed time between two reloads
of the counter depends on the Watchdog timeout
period.
The Output mode should not be enabled, since in
this context it is meaningless.
Figure 56. Watchdog Timer Mode
COUNT
VALUE
TIMER START COUNTING
RESET
WRITE WDTRH,WDTRL
SOFTWARE FAIL
G
WD EN=0
(E.G. INFINITE LOOP)
OR PERIPHERAL FAIL
WRITE AAh,55h
INTOWDTRL
PRODUCE
COUNT RELOAD
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ETC [ ETC ]
