ST90158 - REGISTER AND MEMORY MAP
Reset
Value
Hex.
Page
Reg.
No.
Register
Name
Block
Description
(Decimal)
R240
R242
R246
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
CLKCTL
CLK_FLAG
PLLCONF
D0R0
Clock Control Register
Clock Flag Register
00
55
RCCU
48, 28 or 08
PLL Configuration Register
Channel 0 Data Register
Channel 1 Data Register
Channel 2 Data Register
Channel 3 Data Register
Channel 4 Data Register
Channel 5 Data Register
Channel 6 Data Register
Channel 7 Data Register
Channel 6 Lower Threshold Reg.
Channel 7 Lower Threshold Reg.
Channel 6 Upper Threshold Reg.
Channel 7 Upper Threshold Reg.
Compare Result Register
Control Logic Register
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
0F
00
0F
x2
D1R0
D2R0
D3R0
D4R0
D5R0
D6R0
D7R0
63
AD0
LT6R0
LT7R0
UT6R0
UT7R0
CRR0
CLR0
ICR0
Interrupt Control Register
Interrupt Vector Register
IVR0
(*) Not present on ST90135.
Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register
description for details.
47/199
9
ETC [ ETC ]
