ST90158 - REGISTER AND MEMORY MAP
Table 8. Detailed Register Map
Reset
Value
Hex.
Page
Reg.
No.
Register
Name
Block
Description
(Decimal)
R230
R231
R232
R233
R234
R235
R236
R237
R238
R239
R224
R225
R226
R228
R229
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R240
R241
R242
R244
R245
R246
R248
R249
R250
CICR
FLAGR
RP0
Central Interrupt Control Register
Flag Register
87
00
xx
Pointer 0 Register
RP1
Pointer 1 Register
xx
PPR
Page Pointer Register
xx
Core
MODER
USPHR
USPLR
SSPHR
SSPLR
P0DR
P1DR
P2DR
P4DR
P5DR
MIRROR
EITR
Mode Register
E0
xx
User Stack Pointer High Register
User Stack Pointer Low Register
System Stack Pointer High Reg.
System Stack Pointer Low Reg.
Port 0 Data Register
N/A
xx
xx
xx
FF
FF
FF
FF
FF
00
00
00
00
FF
x6
00
FF
FF
FF
12
7F
xx
I/O
Port
Port 1 Data Register
Port 2 Data Register
5:4,2:0
Port 4 Data Register
Port 5 Data Register
MR
INT
Mirror register
External Interrupt Trigger Register
External Interrupt Pending Reg.
External Interrupt Mask-bit Reg.
External Interrupt Priority Level Reg.
External Interrupt Vector Register
Nested Interrupt Control
EIPR
EIMR
EIPLR
EIVR
NICR
0
WDTHR
WDTLR
WDTPR
WDTCR
WCR
Watchdog Timer High Register
Watchdog Timer Low Register
Watchdog Timer Prescaler Reg.
Watchdog Timer Control Register
Wait Control Register
WDT
SPI
SPIDR
SPICR
P0C0
SPI Data Register
SPI Control Register
00
00
00
00
00
00
00
FF
00
00
Port 0 Configuration Register 0
Port 0 Configuration Register 1
Port 0 Configuration Register 2
Port 1 Configuration Register 0
Port 1 Configuration Register 1
Port 1 Configuration Register 2
Port 2 Configuration Register 0
Port 2 Configuration Register 1
Port 2 Configuration Register 2
I/O
Port
0
P0C1
P0C2
P1C0
I/O
Port
1
2
P1C1
P1C2
P2C0
I/O
Port
2
P2C1
P2C2
42/199
9
ETC [ ETC ]
