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ST72254G1B1 参数 Datasheet PDF下载

ST72254G1B1图片预览
型号: ST72254G1B1
PDF下载: 下载PDF文件 查看货源
内容描述: 与单电压闪存的8位MCU 。 ADC。 16位定时器。 SPI 。\n [8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY. ADC. 16-BIT TIMERS. SPI. ]
分类和应用: 闪存
文件页数/大小: 140 页 / 1350 K
品牌: ETC [ ETC ]
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ST72104G, ST72215G, ST72216G, ST72254G  
Register  
Label  
Reset  
Status  
Address  
Block  
Register Name  
Remarks  
R/W  
0031h  
0032h  
0033h  
0034h  
0035h  
0036h  
0037h  
0038h  
0039h  
003Ah  
003Bh  
003Ch  
003Dh  
003Eh  
003Fh  
TACR2  
TACR1  
TASR  
TAIC1HR  
TAIC1LR  
TAOC1HR  
TAOC1LR  
TACHR  
Timer A Control Register 2  
Timer A Control Register 1  
Timer A Status Register  
Timer A Input Capture 1 High Register  
Timer A Input Capture 1 Low Register  
Timer A Output Compare 1 High Register  
Timer A Output Compare 1 Low Register  
Timer A Counter High Register  
00h  
00h  
xxh  
xxh  
xxh  
80h  
00h  
FFh  
FCh  
FFh  
FCh  
xxh  
xxh  
80h  
00h  
R/W  
Read Only  
Read Only  
Read Only  
R/W  
R/W  
TIMER A  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
R/W  
TACLR  
Timer A Counter Low Register  
TAACHR  
TAACLR  
TAIC2HR  
TAIC2LR  
TAOC2HR  
TAOC2LR  
Timer A Alternate Counter High Register  
Timer A Alternate Counter Low Register  
Timer A Input Capture 2 High Register  
Timer A Input Capture 2 Low Register  
Timer A Output Compare 2 High Register  
Timer A Output Compare 2 Low Register  
R/W  
0040h  
MISCR2  
Miscellaneous Register 2  
00h  
R/W  
0041h  
0042h  
0043h  
0044h  
0045h  
0046h  
0047h  
0048h  
0049h  
004Ah  
004Bh  
004Ch  
004Dh  
004Eh  
004Fh  
TBCR2  
TBCR1  
TBSR  
TBIC1HR  
TBIC1LR  
TBOC1HR  
TBOC1LR  
TBCHR  
Timer B Control Register 2  
Timer B Control Register 1  
Timer B Status Register  
Timer B Input Capture 1 High Register  
Timer B Input Capture 1 Low Register  
Timer B Output Compare 1 High Register  
Timer B Output Compare 1 Low Register  
Timer B Counter High Register  
00h  
00h  
xxh  
xxh  
xxh  
80h  
00h  
FFh  
FCh  
FFh  
FCh  
xxh  
xxh  
80h  
00h  
R/W  
R/W  
Read Only  
Read Only  
Read Only  
R/W  
R/W  
TIMER B  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
R/W  
TBCLR  
Timer B Counter Low Register  
TBACHR  
TBACLR  
TBIC2HR  
TBIC2LR  
TBOC2HR  
TBOC2LR  
Timer B Alternate Counter High Register  
Timer B Alternate Counter Low Register  
Timer B Input Capture 2 High Register  
Timer B Input Capture 2 Low Register  
Timer B Output Compare 2 High Register  
Timer B Output Compare 2 Low Register  
R/W  
0050h  
to  
Reserved (32 Bytes)  
006Fh  
0070h  
0071h  
ADCDR  
ADCCSR  
Data Register  
Control/Status Register  
00h  
00h  
Read Only  
R/W  
ADC  
0072h  
to  
Reserved (14 Bytes)  
007Fh  
Legend: x=undefined, R/W=read/write  
Notes:  
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-  
tion, the values of the I/O pins are returned instead of the DR register contents.  
2. The bits associated with unavailable pins must always keep their reset value.  
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