ST72104G, ST72215G, ST72216G, ST72254G
Table 2. Hardware Register Map
Register
Reset
Status
Address
Block
Register Name
Port C Data Register
Port C Data Direction Register
Port C Option Register
Remarks
Label
1)
2)
0000h
0001h
0002h
PCDR
PCDDR
PCOR
00h
R/W
2)
2)
Port C
00h
00h
R/W
R/W
0003h
Reserved (1 Byte)
1)
0004h
0005h
0006h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
R/W
R/W
R/W.
Port B
Port A
00h
00h
0007h
Reserved (1 Byte)
1)
R/W
R/W
0008h
0009h
000Ah
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
00h
00h
R/W
000Bh
to
Reserved (21 Bytes)
001Fh
0020h
MISCR1
Miscellaneous Register 1
00h
R/W
0021h
0022h
0023h
SPIDR
SPICR
SPISR
SPI Data I/O Register
SPI Control Register
SPI Status Register
xxh
0xh
00h
R/W
R/W
Read Only
SPI
0024h
0025h
WATCHDOG WDGCR
CRSR
Watchdog Control Register
7Fh
R/W
Clock, Reset, Supply Control / Status Register 000x 000x R/W
Reserved (2 bytes)
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
Control Register
Status Register 1
Status Register 2
Clock Control Register
Own Address Register 1
Own Address Register 2
Data Register
00h
00h
00h
00h
00h
00h
00h
R/W
Read Only
Read Only
R/W
R/W
R/W
2
I C
R/W
002Fh
to
Reserved (4 Bytes)
0030h
11/140
ETC [ ETC ]
