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PIC16F877T-20PQ 参数 Datasheet PDF下载

PIC16F877T-20PQ图片预览
型号: PIC16F877T-20PQ
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器\n [8-Bit Microcontroller ]
分类和应用: 微控制器
文件页数/大小: 200 页 / 3338 K
品牌: ETC [ ETC ]
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PIC16F87X  
A PWM output (Figure 8-4) has a time-base (period)  
and a time that the output stays high (duty cycle). The  
frequency of the PWM is the inverse of the period  
(1/period).  
The CCPR1H register and a 2-bit internal latch are  
used to double buffer the PWM duty cycle. This double  
buffering is essential for glitchless PWM operation.  
When the CCPR1H and 2-bit latch match TMR2 con-  
catenated with an internal 2-bit Q clock or 2 bits of the  
TMR2 prescaler, the CCP1 pin is cleared.  
FIGURE 8-4: PWM OUTPUT  
Maximum PWM resolution (bits) for a given PWM  
frequency:  
Period  
FOSC  
log( )  
FPWM  
Resolution  
bits  
=
Duty Cycle  
TMR2 = PR2  
log(2)  
Note: If the PWM duty cycle value is longer than  
the PWM period, the CCP1 pin will not be  
cleared.  
TMR2 = Duty Cycle  
TMR2 = PR2  
8.3.3  
SET-UP FOR PWM OPERATION  
8.3.1  
PWM PERIOD  
The following steps should be taken when configuring  
the CCP module for PWM operation:  
The PWM period is specified by writing to the PR2 reg-  
ister. The PWM period can be calculated using the fol-  
lowing formula:  
1. Set the PWM period by writing to the PR2 register.  
2. Set the PWM duty cycle by writing to the  
CCPR1L register and CCP1CON<5:4> bits.  
PWM period = [(PR2) + 1] • 4 • TOSC •  
(TMR2 prescale value)  
3. Make the CCP1 pin an output by clearing the  
TRISC<2> bit.  
PWM frequency is defined as 1 / [PWM period].  
When TMR2 is equal to PR2, the following three events  
occur on the next increment cycle:  
4. Set the TMR2 prescale value and enable Timer2  
by writing to T2CON.  
5. Configure the CCP1 module for PWM operation.  
• TMR2 is cleared  
• The CCP1 pin is set (exception: if PWM duty  
cycle = 0%, the CCP1 pin will not be set)  
• The PWM duty cycle is latched from CCPR1L into  
CCPR1H  
Note: The Timer2 postscaler (see Section 8.1) is  
not used in the determination of the PWM  
frequency. The postscaler could be used to  
have a servo update rate at a different fre-  
quency than the PWM output.  
8.3.2  
PWM DUTY CYCLE  
The PWM duty cycle is specified by writing to the  
CCPR1L register and to the CCP1CON<5:4> bits. Up  
to 10-bit resolution is available. The CCPR1L contains  
the eight MSbs and the CCP1CON<5:4> contains the  
two LSbs. This 10-bit value is represented by  
CCPR1L:CCP1CON<5:4>. The following equation is  
used to calculate the PWM duty cycle in time:  
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •  
Tosc • (TMR2 prescale value)  
CCPR1L and CCP1CON<5:4> can be written to at any  
time, but the duty cycle value is not latched into  
CCPR1H until after a match between PR2 and TMR2  
occurs (i.e., the period is complete). In PWM mode,  
CCPR1H is a read-only register.  
1999 Microchip Technology Inc.  
DS30292B-page 61  
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