PIC16F87X
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
8.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
Note: The special event trigger from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
• Driven high
• Driven low
• Remains unchanged
8.3
PWM Mode (PWM)
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
In pulse width modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
FIGURE 8-2: COMPARE MODE OPERATION
BLOCK DIAGRAM
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Special Event Trigger
Figure 8-3 shows a simplified block diagram of the CCP
module in PWM mode.
Set flag bit CCP1IF
(PIR1<2>)
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3.
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
match
RC2/CCP1
Pin
FIGURE 8-3: SIMPLIFIED PWM BLOCK
DIAGRAM
TRISC<2>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
8.2.1
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
CCPR1H (Slave)
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
Q
R
S
Comparator
8.2.2
TIMER1 MODE SELECTION
RC2/CCP1
(Note 1)
TMR2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
8.2.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
8.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
DS30292B-page 60
1999 Microchip Technology Inc.
ETC [ ETC ]
