PIC16F87X
FIGURE 10-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
Start
bit
Start
bit
RC7/RX/DT (pin)
bit0
bit1
Stop
bit
bit8 Stop
bit
bit0
bit8
Load RSR
Read
WORD 1
RCREG
Bit8 = 0, Data Byte
Bit8 = 1, Address Byte
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(receive buffer) because ADDEN = 1.
FIGURE 10-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
Start
bit
Start
bit
RC7/RX/DT (pin)
bit0
bit1
Stop
bit
bit8 Stop
bit
bit0
bit8
Load RSR
Read
WORD 1
RCREG
Bit8 = 1, Address Byte
Bit8 = 0, Data Byte
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(receive buffer) because ADDEN was not updated and still = 0.
TABLE 10-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
RCREG USART Receive Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
DS30292B-page 104
1999 Microchip Technology Inc.
ETC [ ETC ]
