PIC16F87X
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
3.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
Three pins of PORTB are multiplexed with the Low Volt-
age Programming function; RB3/PGM, RB6/PGC and
RB7/PGD. The alternate functions of these pins are
described in the Special Features Section.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
This interrupt on mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
FIGURE 3-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
VDD
RBPU(2)
weak
pull-up
RB0/INT is discussed in detail in Section 12.10.1.
P
Data Latch
Data Bus
WR Port
D
Q
FIGURE 3-4: BLOCK DIAGRAM OF
I/O
pin(1)
RB7:RB4 PINS
CK
TRIS Latch
VDD
RBPU(2)
weak
P
D
Q
pull-up
TTL
Data Latch
Data Bus
Input
Buffer
WR TRIS
CK
D
Q
I/O
pin(1)
WR Port
CK
TRIS Latch
RD TRIS
RD Port
D
Q
Q
D
WR TRIS
TTL
Input
Buffer
CK
EN
ST
Buffer
RB0/INT
RB3/PGM
RD TRIS
RD Port
Latch
Schmitt Trigger
Buffer
RD Port
Q
Q
D
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
EN
Q1
Set RBIF
D
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
From other
RB7:RB4 pins
RD Port
Q3
EN
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
Note: When using Low Voltage ICSP Programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the
TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device.
1999 Microchip Technology Inc.
DS30292B-page 31
ETC [ ETC ]
