PIC16F87X
2
Development Support ......................................................145
Device Differences ...........................................................183
Device Overview ..................................................................5
Direct Addressing ......................................................... 27, 28
I C Module Address Register, SSPADD ........................... 72
I C Slave Mode .................................................................. 72
2
ID Locations ............................................................. 121, 135
In-Circuit Serial Programming (ICSP) ...................... 121, 136
INDF .................................................................................. 17
INDF Register ........................................................ 15, 16, 27
Indirect Addressing ...................................................... 27, 28
FSR Register ............................................................. 12
Instruction Format ............................................................ 137
Instruction Set .................................................................. 137
ADDLW .................................................................... 139
ADDWF .................................................................... 139
ANDLW .................................................................... 139
ANDWF .................................................................... 139
BCF ......................................................................... 139
BSF .......................................................................... 139
BTFSC ..................................................................... 140
BTFSS ..................................................................... 140
CALL ........................................................................ 140
CLRF ....................................................................... 140
CLRW ...................................................................... 140
CLRWDT ................................................................. 140
COMF ...................................................................... 141
DECF ....................................................................... 141
DECFSZ .................................................................. 141
GOTO ...................................................................... 141
INCF ........................................................................ 141
INCFSZ .................................................................... 141
IORLW ..................................................................... 142
IORWF ..................................................................... 142
MOVF ...................................................................... 142
MOVLW ................................................................... 142
MOVWF ................................................................... 142
NOP ......................................................................... 142
RETFIE .................................................................... 143
RETLW .................................................................... 143
RETURN .................................................................. 143
RLF .......................................................................... 143
RRF ......................................................................... 143
SLEEP ..................................................................... 143
SUBLW .................................................................... 144
SUBWF .................................................................... 144
SWAPF .................................................................... 144
XORLW ................................................................... 144
XORWF ................................................................... 144
Summary Table ....................................................... 138
INTCON ............................................................................. 17
INTCON Register ............................................................... 20
GIE Bit ....................................................................... 20
INTE Bit ..................................................................... 20
INTF Bit ..................................................................... 20
PEIE Bit ..................................................................... 20
RBIE Bit ..................................................................... 20
RBIF Bit ............................................................... 20, 31
T0IE Bit ...................................................................... 20
T0IF Bit ...................................................................... 20
E
Electrical Characteristics ..................................................151
Errata ...................................................................................4
F
Firmware Instructions .......................................................137
FSR Register ....................................................15, 16, 17, 27
G
General Call Address Sequence ........................................74
General Call Address Support ...........................................74
General Call Enable bit ......................................................66
I
I/O Ports .............................................................................29
2
I C ......................................................................................71
2
I C Master Mode Reception ...............................................83
2
I C Master Mode Restart Condition ...................................80
2
I C Mode Selection ............................................................71
2
I C Module
Acknowledge Sequence timing ..................................85
Addressing .................................................................72
Baud Rate Generator .................................................78
Block Diagram ............................................................76
BRG Block Diagram ...................................................78
BRG Reset due to SDA Collision ...............................90
BRG Timing ...............................................................78
Bus Arbitration ...........................................................88
Bus Collision ..............................................................88
Acknowledge ......................................................88
Restart Condition ...............................................91
Restart Condition Timing (Case1) ......................91
Restart Condition Timing (Case2) ......................91
Start Condition ...................................................89
Start Condition Timing ................................. 89, 90
Stop Condition ...................................................92
Stop Condition Timing (Case1) ..........................92
Stop Condition Timing (Case2) ..........................92
Transmit Timing .................................................88
Bus Collision timing ....................................................88
Clock Arbitration .........................................................87
Clock Arbitration Timing (Master Transmit) ................87
Conditions to not give ACK Pulse ..............................72
General Call Address Support ...................................74
Master Mode ..............................................................76
Master Mode 7-bit Reception timing ..........................84
Master Mode Operation .............................................77
Master Mode Start Condition .....................................79
Master Mode Transmission ........................................81
Master Mode Transmit Sequence ..............................77
Multi-Master Communication .....................................88
Multi-master Mode .....................................................77
Operation ...................................................................71
Repeat Start Condition timing ....................................80
Slave Mode ................................................................72
Slave Reception .........................................................73
Slave Transmission ....................................................73
SSPBUF .....................................................................72
Stop Condition Receive or Transmit timing ................86
Stop Condition timing .................................................86
Waveforms for 7-bit Reception ..................................73
Waveforms for 7-bit Transmission .............................74
2
Inter-Integrated Circuit (I C) .............................................. 63
Internal Sampling Switch (Rss) Impedence ..................... 114
Interrupt Sources ..................................................... 121, 131
Block Diagram ......................................................... 131
Interrupt on Change (RB7:RB4 ) ............................... 31
RB0/INT Pin, External ...................................... 7, 8, 132
TMR0 Overflow ........................................................ 132
USART Receive/Transmit Complete ......................... 95
DS30292B-page 186
1999 Microchip Technology Inc.
ETC [ ETC ]
