PIC16F87X
REGISTER 9-2:
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
R/W-0
SSPOV
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ‘0’
WCOL
bit7
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit0
- n = Value at POR reset
bit 7:
WCOL: Write Collision Detect bit
Master Mode:
2
1 = A write to SSPBUF was attempted while the I C conditions were not valid
0 = No collision
Slave Mode:
1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while SSPBUF holds previous data. Data in SSPSR is lost on overflow. . In
slave mode the user must read the SSPBUF, even if only transmitting data, to avoid overflows. In master
mode the overflow bit is not set since each operation is initiated by writing to the SSPBUF register. (Must
be cleared in software).
0 = No overflow
2
In I C mode
1 = A byte is received while the SSPBUF is holding the previous byte. SSPOV is a "don’t care" in trans-
mit mode. (Must be cleared in software).
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode, when enabled, these pins must be properly configured as input or output.
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
2
In I C mode, when enabled, these pins must be properly configured as input or output.
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
2
In I C slave mode, SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
2
In I C master mode
Unused in this mode
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = FOSC/4
0001 = SPI master mode, clock = FOSC/16
0010 = SPI master mode, clock = FOSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
2
0110 = I C slave mode, 7-bit address
2
0111 = I C slave mode, 10-bit address
2
1000 = I C master mode, clock = FOSC / (4 * (SSPADD+1) )
2
1011 = I C firmware controlled master mode (slave idle)
2
1110 = I C firmware controlled master mode, 7-bit address with start and stop bit interrupts enabled
2
1111 = I C firmware controlled master mode, 10-bit address with start and stop bit interrupts enabled.
1001, 1010, 1100, 1101 = reserved
1999 Microchip Technology Inc.
DS30292B-page 65
ETC [ ETC ]
