PIC16F87X
REGISTER 9-3:
SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h)
R/W-0
GCEN
R/W-0
ACKSTAT
R/W-0
ACKDT
R/W-0
ACKEN
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Read as ‘0’
- n =Value at POR reset
bit 7:
GCEN:
General Call Enable bit (In I
2
C slave mode only)
1
= Enable interrupt when a general call address (0000h) is received in the SSPSR.
0
= General call address disabled.
ACKSTAT:
Acknowledge Status bit (In I
2
C master mode only)
In master transmit mode:
1
= Acknowledge was not received from slave
0
= Acknowledge was received from slave
ACKDT:
Acknowledge Data bit (In I
2
C master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
1
= Not Acknowledge
0
= Acknowledge
ACKEN:
Acknowledge Sequence Enable bit (In I
2
C master mode only).
In master receive mode:
1
= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically
cleared by hardware.
0
= Acknowledge sequence idle
RCEN:
Receive Enable bit (In I
2
C master mode only).
1
= Enables Receive mode for I
2
C
0
= Receive idle
PEN:
Stop Condition Enable bit (In I
2
C master mode only).
SCK release control
1
= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0
= Stop condition idle
RSEN:
Repeated Start Condition Enabled bit (In I
2
C master mode only)
1
= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0
= Repeated Start condition idle.
SEN:
Start Condition Enabled bit (In I
2
C master mode only)
1
= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0
= Start condition idle.
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
2
C module is not in the idle mode, this bit may not
be set (no spooling), and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
Note:
ã
DS30292B-page 66
1999 Microchip Technology Inc.
ETC [ ETC ]
