CAT28C512/513
512K-Bit CMOS PARALLEL EEPROM
FEATURES
s
Fast Read Access Times: 120/150 ns
s
Low Power CMOS Dissipation:
s
Automatic Page Write Operation:
–Active: 50 mA Max.
–Standby: 200
µ
A Max.
s
Simple Write Operation:
–1 to 128 Bytes in 5ms
–Page Load Timer
s
End of Write Detection:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s
Fast Write Cycle Time:
–Toggle Bit
–DATA Polling
DATA
s
Hardware and Software Write Protection
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
s
Commercial, Industrial and Automotive
–5ms Max
s
CMOS and TTL Compatible I/O
Temperature Ranges
DESCRIPTION
The CAT28C512/513 is a fast,low power, 5V-only CMOS
parallel EEPROM organized as 64K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA
Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C512/513 features hardware and software write
protection.
The CAT28C512/513 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 32-pin DIP, PLCC, 32-pin TSOP and 40-pin
TSOP packages.
BLOCK DIAGRAM
A7–A15
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
65,536 x 8
E
2
PROM
ARRAY
128 BYTE PAGE
REGISTER
VCC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
I/O BUFFERS
TIMER
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
5096 FHD F02
I/O0–I/O7
A0–A6
ADDR. BUFFER
& LATCHES
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1007, Rev. A
ETC [ ETC ]
