Absolute Maximum Ratings (Ta=25˚C)
Parameter
Power supply voltage
Output voltage
Nch open drain output
CMOS output
Symbol
VDD – GND
V
OUT
V
CT
Pd
Pd
Topr
Tstg
Input voltage of CT
Power dissipation:
SSOP5
(SMP5C2)
*
1
Power dissipation:
VSOF5
(EMP5)
*
2
Operating temperature range
Storage temperature range
Limits
– 0.3 ~ + 10
GND – 0.3 ~ + 10
GND – 0.3 ~ VDD + 0.3
GND – 0.3 ~ VDD + 0.3
540
210
– 40 ~ + 85
– 55 ~ + 125
Unit
V
V
V
mW
mW
˚C
˚C
*
1
Derating: 5.4mW/
˚C
for operation above Ta=25
˚C
.(Mounted on a 70.0mmX70.0mmX16mm glass epoxy PCB.)
*
2
Derating: 2.1mW/
˚C
for operation above Ta=25
˚C
.(Mounted on a 70.0mmX70.0mmX16mm glass epoxy PCB.)
Electrical characteristics (
Unless otherwise noted; Ta=-25~85˚C)
Parameter
Detection voltage
temperature coefficient
*1
Symbol
Min.
Typ.
±100
VsX0.05
0.80
0.85
0.90
0.95
0.75
0.80
0.85
0.90
—
1.2
5.0
1.4
1.8
2.2
—
V
DD
X0.4
V
DD
X0.45
V
DD
X0.5
V
DD
X0.5
9
40
240
Max.
Unit
Conditions
L
V
DET
=2.3~3.1V
V
DET
=3.2~4.2V
V
DD
=V
DET
–0.2V
V
DET
=4.3~5.2V
V
DET
=5.3~6.0V
V
DET
=2.3~3.1V
V
DET
=3.2~4.2V
V
DD
=V
DET
+2V
V
DET
=4.3~5.2V
V
DET
=5.3~6.0V
R
L
=470kΩ, V
OL
≥
0.4V
V
DS
=0.5V, V
DD
=1.2V
V
DS
=0.5V, V
DD
=2.4V (V
DET
≥
2.7V)
V
DS
=0.5V, V
DD
=4.8V V
DET
=2.3~4.2V
V
DS
=0.5V, V
DD
=6.0V V
DET
=4.3~5.2V
V
DS
=0.5V, V
DD
=8.0V V
DET
=5.3~6.0V
V
DD
=V
DS
=10V
V
DET
=2.3~2.6V
V
DET
=2.7~4.2V
V
DD
=V
DET
X1.1
V
DET
=4.3~5.2V
V
DET
=5.3~6.0V
V
DD
=V
DET
X1.1
V
CT
=0.1V,V
DD
=0.95V
V
CT
=0.5V,V
DD
=1.5V
RL=470kΩ, V
DD
=L
H
Hysteresis voltage
Circuit current when ON
Circuit current when OFF
Min. operating voltage
"L" output current
"H" output current
Output leak current
*1
CT pin Threshold voltage
Output delay resistance
*1
CT pin output current
*1
—
V
DET
/∆T
∆V
DET
VsX0.03
—
—
Icc1
—
—
—
—
Icc2
—
—
V
OPL
0.95
0.4
I
OL
2.0
0.7
I
OH
0.9
1.1
Ileak
—
V
DD
X0.3
V
CTH
V
DD
X0.3
V
DD
X0.35
V
DD
X0.4
R
CT
5.5
15
I
CT
150
±360
ppm/ ˚C
VsX0.08
%
2.40
2.55
µA
2.70
2.85
2.25
2.40
µA
2.55
2.70
—
V
—
mA
—
—
mA
—
—
0.1
µA
V
DD
X0.6
V
DD
X0.6
V
V
DD
X0.6
V
DD
X0.6
12.5
MΩ
—
µA
—
*1 This value is guranteed at Ta=25˚C.
*2 T
PLH
: V
DD
=(V
DET
typ.–0.5V)
(V
DET
typ.+0.5V).
Note) RL is not necessary for CMOS output type.
Note) Please refer to the detection voltage of Line-up table.
Characteristic diagram and Measurement circuit
10
1
Output delay time "L
[BD5242G/FVE]
H"
40.00
35.00
30.00
Output delay time "H
L"
[BD5242G/FVE]
delay time[s]
delay time[µs]
0.1
0.01
0.001
0.0001
0.00001
0.000001
0.0001
0.001
0.01
0.1
1
25.00
20.00
15.00
10.00
5.00
0.00
0.0001
0.0010
0.0100
0.1000
1.0000
CT Capacitance [µF]
5V
R
L
=100kΩ
V
DD
CT
V
DET
0.5V
GND
100pF
V
OUT
V
DET
0.5V
CT Capacitance[µF]
5V
R
L
=100kΩ
V
DD
CT
GND
100pF
V
OUT
ETC [ ETC ]
