TIMING DIAGRAMS AND TEST CIRCUITS
1.4V
3kΩ
D
OUT
100pF
C
LOAD
Test Point
D
OUT
t
r
t
f
V
OH
V
OL
Load Circuit for t
dDO
, t
r
, and t
f
Voltage Waveforms for D
OUT
Rise and Fall Times t
r
, and t
f
Test Point
DCLOCK
V
IL
t
dDO
D
OUT
t
hDO
Voltage Waveforms for D
OUT
Delay Times, t
dDO
Load Circuit for t
dis
and t
den
V
CC
V
OH
V
OL
D
OUT
3kΩ
100pF
C
LOAD
t
dis
Waveform 2, t
en
t
dis
Waveform 1
CS/SHDN
V
IH
CS/SHDN
D
OUT
Waveform 1
(1)
t
dis
D
OUT
Waveform 2
(2)
Voltage Waveforms for t
dis
90%
DCLOCK
1
2
10%
D
OUT
t
en
V
OL
B11
NOTES: (1) Waveform 1 is for an output with internal conditions such that
the output is HIGH unless disabled by the output control. (2) Waveform 2
is for an output with internal conditions such that the output is LOW unless
disabled by the output control.
Voltage Waveforms for t
en
®
ADS1286
8
ETC [ ETC ]
