欢迎访问ic37.com |
会员登录 免费注册
发布采购

UC2895 参数 Datasheet PDF下载

UC2895图片预览
型号: UC2895
PDF下载: 下载PDF文件 查看货源
内容描述: BiCMOS工艺Adbanced相移PWM控制器 [BiCMOS Adbanced Phase Shift PWM Controller]
分类和应用: 控制器
文件页数/大小: 11 页 / 177 K
品牌: ETC [ ETC ]
 浏览型号UC2895的Datasheet PDF文件第1页浏览型号UC2895的Datasheet PDF文件第2页浏览型号UC2895的Datasheet PDF文件第3页浏览型号UC2895的Datasheet PDF文件第5页浏览型号UC2895的Datasheet PDF文件第6页浏览型号UC2895的Datasheet PDF文件第7页浏览型号UC2895的Datasheet PDF文件第8页浏览型号UC2895的Datasheet PDF文件第9页  
UCC1895
UCC2895
UCC3895
RDELCD=10kΩ, C
REF
=0.1
µ
F, C
VDD
=1.0
µ
F, no load at outputs. T
A
= T
J
. T
A
= 0°C to 70°C for UCC3895x, –40°C to +85°C for
UCC2895x, and –55°C to +125°C for UCC1895x.
PARAMETER
Soft Start/Shutdown Section
Soft Start Source Current
Soft Start Sink Current
Soft Start/Disable Comparator Threshold
Delay Set Section
DELAB/DELCD Output Voltage
Output Delay
ADS Bias Current
Output Section
VOH (all outputs)
VOL (all outputs)
Rise TIme
Fall Time
IOUT = –10mA, VDD to Output
IOUT = 10mA
C
LOAD
= 100pF
C
LOAD
= 100pF
250
150
20
20
400
250
35
35
mV
mV
ns
ns
ADS = CS = 0V
ADS = 0V, CS = 2.0V
ADS = CS = 0V (Note 2)
0V < ADS < 2.5V, 0V < CS < 2.5V
0.45
1.9
450
–20
0.50
2.0
525
0.55
2.1
600
20
V
V
ns
SS/DISB = 3.0V, CS < 1.9V
SS/DISB = 3.0V, CS > 2.6V
–40
325
0.44
–35
350
0.50
–30
375
0.56
TEST CONDITIONS
MIN
TYP
MAX UNITS
ELECTRICAL CHARACTERISTICS:
Unless otherwise specified, VDD=12V, RT=82kΩ, CT=220pF, RDELAB=10kΩ,
µ
A
µ
A
V
µ
A
Note 1: Minimum phase shift is defined as followed:
Φ =
200
t
f
(
OUTA
)
t
f
(
OUTC
)
t
PERIOD
t
f
(
OUTB
)
t
f
(
OUTD
)
t
PERIOD
t
PERIOD
Or
OUTA
t
DELAY
= t
f(OUTA)
– t
f(OUTC)
Φ =
200
where
t
f(OUTA)
= falling edge of OUTA signal
t
f(OUTB)
= falling edge of OUTB signal
t
f(OUTC)
= falling edge of OUTC signal
t
f(OUTD)
= falling edge of OUTD signal
t
(PERIOD)
= period of OUTA or OUTB signal
Same applies to OUTB and OUTD
OUTC
Note 2. Output delay is measured between OUTA/OUTB or
OUTC/OUTD. Output delay is defined as shown below,
where:
t
f(OUTA)
= falling edge of OUTA signal
t
r(OUTB)
= rising edge of OUTB signal
Note 3: Guaranteed by design. Not 100% tested in production.
OUTA
t
DELAY
= t
f(OUTA)
– t
r(OUTB)
OUTB
Same applies to OUTC and OUTD
4