R
×
5VL
Output Delay Time t
PLH
is defined as follows:
1. In the case of Nch Open Drain Output:
When the time at which a pulse voltage which increases from 1.2V to +V
DET
+2.0V is applied to V
DD
is
Time A, and the time at which the output reaches 3.5V under the conditions that the output pin (OUT)
is pulled up to 7V by a resistor of 100kΩ is Time B, the time period from Time A through Time B.
2. In the case of CMOS Output:
When the time at which a pulse voltage which increases from 1.2V to +V
DET
+2.0V is applied to V
DD
is
Time A, and the time at which the output voltage reaches the voltage of (+V
DET
+2.0V)/2 is Time B, the
time period from Time A through Time B.
3