BC846 thru BC849
0.30 (7.5)
0.12 (3)
Vishay Semiconductors
formerly General Semiconductor
Layout for R
ΘJA
test
Thickness:
Fiberglass 0.059 in. (1.5 mm)
Copper leads 0.012 in. (0.3 mm)
.04 (1)
.08 (2)
.04 (1)
.08 (2)
0.59 (15)
0.47 (12)
0.03 (0.8)
Dimensions in inches (millimeters)
0.2 (5)
Admissible power dissipation
versus temperature of substrate backside
Device on fiblerglass substrate, see layout
0.06 (1.5)
0.20 (5.1)
Pulse thermal resistance
versus pulse duration (normalized)
Device on fiblerglass substrate, see layout
DC current gain versus collector current
Collector-Base cutoff current versus
ambient temperature
Document Number 88164
09-May-02
www.vishay.com
3