TPS3809J25, TPS3809L30, TPS3809K33, TPS3809I50
3-PIN SUPPLY VOLTAGE SUPERVISORS
SLVS228 – AUGUST 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
High-level output voltage
TEST CONDITIONS
VDD = 2.5 V to 6 V,
VDD = 3.3 V,
VDD = 6 V,
VDD = 2 V to 6 V,
VOL
Low-level output voltage
Power-up reset voltage (see Note 2)
TPS3809J25
VIT
IT–
Negative-going input threshold
g
g g
voltage (see Note 3)
TPS3809L30
TPS3809K33
TPS3809I50
TPS3809J25
Vh
hys
Hysteresis
TPS3809L30
TPS3809K33
TPS3809I50
IDD
Ci
Supply current
Input capacitance
VDD = 2 V, Output unconnected
VDD = 6 V, Output unconnected
TA– 40°C to 85°C
VDD = 3.3 V,
VDD = 6 V,
VDD
≥
1.1 V,
IOH = –500
µA
IOH = –2 mA
IOH = –4 mA
IOL = 500
µA
IOL = 2 mA
IOL = 4 mA
IOL = 50
µA
2.20
2.58
2.87
4.45
2.25
2.64
2.93
4.55
30
35
40
60
9
20
12
25
µA
mV
MIN
VDD –0.2
VDD –0.4
VDD –0.4
0.2
0.4
0.4
0.2
2.30
2.70
2.99
4.65
V
V
V
TYP
MAX
UNIT
V
VI = 0 V to VDD
5
pF
NOTES: 2. The lowest supply voltage at which RESET becomes active. tr, VDD
≥
15
µs/V.
3. To ensure best stability of the threshold voltage, a bypass capacitor ( 0.1
µF
ceramic) should be placed near the supply terminals.
timing requirements at R
L
= 1 MΩ, C
L
= 50 pF, T
A
= 25°C
PARAMETER
tw
Pulse width
at VDD
VDD = VIT– + 0.2 V,
TEST CONDITIONS
VDD = VIT– – 0.2 V
MIN
3
TYP
MAX
UNIT
µs
switching characteristics at R
L
= 1 MΩ, C
L
= 50 pF, T
A
= 25°C
PARAMETER
td
tPHL
Delay time
Propagation (delay) time, high-to-low-level output
VDD to RESET delay
TEST CONDITIONS
VDD
≥
VIT– + 0.2 V,
See timing diagram
VIL = VIT– – 0.2 V,
VIH = VIT– +0.2 V
MIN
120
TYP
200
1
MAX
280
UNIT
ms
µs
4
POST OFFICE BOX 655303
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