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OR2C10A-2BA240I 参数 Datasheet PDF下载

OR2C10A-2BA240I图片预览
型号: OR2C10A-2BA240I
PDF下载: 下载PDF文件 查看货源
内容描述: 现场可编程门阵列 [Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列
文件页数/大小: 192 页 / 2992 K
品牌: ETC [ ETC ]
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Data Sheet  
June 1999  
ORCA Series 2 FPGAs  
Programmable Logic Cells (continued)  
F5M and F5X Modes—Special Function Modes  
C0  
F3  
The PFU contains logic to implement two special func-  
tion modes which are variations on the F5 mode. As  
with the F5 mode, the LUT implements two indepen-  
dent five-input functions. Figure 6 and Figure 7 show  
the schematics for F5M and F5X modes, respectively.  
The F5X and F5M functions differ from the basic F5A/  
F5B functions in that there are three logic gates which  
have inputs from the two 5-input LUT outputs. In some  
cases, this can be used for faster and/or wider logic  
functions.  
A4  
A3  
A2  
A1  
A0  
A4  
A3  
A2  
A1  
A0  
QLUT3  
QLUT2  
F2  
F3  
B4  
B3  
B2  
B1  
B0  
B4  
B3  
B2  
B1  
B0  
QLUT1  
QLUT0  
F1  
F0  
As can be seen, two of the three inputs into the NAND,  
XOR, and MUX gates, F0 and F3, are from the LUT.  
The third input is from the C0 input into PFU. Since the  
C0 input bypasses the LUTs, it has a much smaller  
delay through the PFU than for all other inputs into the  
special PFU gates. This allows multiple PFUs to be  
cascaded together while reducing the delay of the criti-  
cal path through the PFUs. The output of the first spe-  
cial function (either XOR or MUX) is F1. Since the XOR  
and MUX share the F1 output, the F5X and F5M  
modes are mutually exclusive. The output of the NAND  
PFU gate is F2 and is always available in either mode.  
F0  
5-2754(F).r3  
Figure 6. F5M Mode—Multiplexed Function of Two  
Independent Five-Input Variable  
Functions  
C0  
F3  
To use either the F5M or F5X functions, the LUT must  
be in the F5A/F5B mode; i.e., only 5-input LUTs  
allowed. In both the F5X and F5M functions, the out-  
puts of the five-input combinatorial functions, F0 and  
F3, are also usable simultaneously with the special  
PFU gate outputs.  
A4  
A3  
A2  
A1  
A0  
A4  
A3  
A2  
A1  
A0  
HLUTA  
F3  
F2  
F1  
The output of the MUX is:  
B4  
B3  
B2  
B1  
B0  
B4  
B3  
B2  
B1  
B0  
HLUTB  
F1 = (HLUTA & C0) + (HLUTB & C0)  
F1 = (F3 & C0) + (F0 & C0)  
F0  
The output of the exclusive OR is:  
F1 = HLUTA HLUTB C0  
F1 = F3 F0 C0  
F0  
5-2755(F).r2  
The output of the NAND is:  
Figure 7. F5X Mode—Exclusive OR Function of Two  
Independent Five-Input Variable  
Functions  
F2 = HLUTA & HLUTB & C0  
F2 = F3 & F0 & C0  
Lucent Technologies Inc.  
9
 
 
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