Specifications
ispLSI 2064/A
Internal Timing Parameters
1
Over Recommended Operating Conditions
PARAMETER
#
2
DESCRIPTION
-125
-100
-80
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs
t
io
t
din
GRP
t
grp
GLB
t
4ptbp
t
4ptbp
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
ORP
t
orp
20
21
Input Buffer Delay
Dedicated Input Delay
–
–
0.2
1.5
–
–
0.5
2.2
–
–
1.8
4.4
ns
ns
22
GRP Delay
–
1.3
–
1.7
–
2.6
ns
23
24
25
26
27
28
29
30
31
32
33
34
35
4 Product Term Bypass Comb. Path Delay
4 Product Term Bypass Reg. Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay
3
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
–
–
–
–
–
–
0.8
3.0
–
–
–
–
3.3
4.5
5.0
5.7
6.0
6.5
0.5
–
–
0.2
1.1
4.8
7.3
5.6
–
–
–
–
–
–
1.2
4.0
–
–
–
–
4.1
5.8
5.8
6.8
7.3
8.0
0.5
–
–
0.3
1.3
6.1
8.6
7.1
–
–
–
–
–
–
1.4
6.0
–
–
–
–
5.6
8.1
6.8
8.0
8.8
9.8
1.3
–
–
0.4
1.6
8.6
9.0
10.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
36
ORP Delay
ORP Bypass Delay
–
–
0.8
0.3
–
–
1.4
0.4
–
–
2.0
0.5
ns
ns
37
t
orpbp
Outputs
38
t
ob
39
t
sl
40
t
oen
41
t
odis
42
t
goe
Clocks
t
gy0
43
t
gy1/2
44
Global Reset
45
t
gr
Output Buffer Delay
Output Slew Limited Delay Adder
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
Global Output Enable
–
–
–
–
–
1.2
10.0
3.2
3.2
3.8
–
–
–
–
–
1.6
10.0
4.2
4.2
4.8
–
–
–
–
–
2.0
10.0
4.6
4.6
7.4
ns
ns
ns
ns
ns
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.3
2.3
2.3
2.3
2.7
2.7
2.7
2.7
3.6
3.6
3.6
3.6
ns
ns
Global Reset to GLB
–
6.9
–
9.2
–
11.4
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2- 0036C/2064-130
6