Specifications
ispLSI 2064/A
Pin Description
NAME
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
GOE 0, GOE 1
Y0, Y1, Y2
RESET
ispEN
TQFP PIN NUMBERS
17,
21,
29,
33,
40,
44,
48,
56,
67,
71,
79,
83,
90,
94,
98,
6,
66,
11,
15
14
18,
22,
30,
34,
41,
45,
53,
57,
68,
72,
80,
84,
91,
95,
3,
7,
87
65,
62
19,
23,
31,
35,
42,
46,
54,
58,
69,
73,
81,
85,
92,
96,
4,
8,
20,
28,
32,
36,
43,
47,
55,
59,
70,
78,
82,
86,
93,
97,
5,
9
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
SDI/IN 0
2
16
MODE/IN 1
2
37
SDO/IN 2
2
39
SCLK/IN 3
2
60
GND
VCC
NC
1
pL
13,
12,
SI
2
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK controls become active.
Input – This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 also is used as one of the two control pins for the ISP state
machine. When ispEN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. When ispEN is logic low, it
functions as a pin to control the operation of the ISP state machine.
When ispEN is high, it functions as a dedicated input pin.
Output/Input – This pin performs two functions. When ispEN is logic
low, it functions as an output pin to read serial shift register data. When
ispEN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
38,
64
2,
26,
51,
75,
99,
06
63,
10,
27,
52,
76,
100
88
24,
49,
61,
77,
is
SE
1,
25,
50,
74,
89,
4E
Ground (GND)
V
CC
No Connect.
FO
R
N
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Active Low (0) Reset pin which resets all of the registers in the device.
EW
Global Output Enable input pins.
U
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
10
D
ES
IG
Table 2-0002-2064b.eps
N
S
ETC [ ETC ]
