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HY57V561620HT-8 参数 Datasheet PDF下载

HY57V561620HT-8图片预览
型号: HY57V561620HT-8
PDF下载: 下载PDF文件 查看货源
内容描述: X16 SDRAM\n [x16 SDRAM ]
分类和应用: 内存集成电路光电二极管动态存储器时钟
文件页数/大小: 13 页 / 174 K
品牌: ETC [ ETC ]
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HY57V561620H(L)T
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
-6
Parameter
Symbol
Min
System clock
cycle time
CAS Latency = 3
CAS Latency = 2
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
tOHZ2
6
1000
10
2.5
2.5
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2
2.7
3
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
5.4
6
7.5
2.5
2.5
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
2.7
2.7
-
-
5.4
5.4
-
-
-
-
-
-
-
-
-
-
5.4
5.4
Max
Min
7.5
1000
10
2.5
2.5
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2
2.7
3
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
5.4
6
Max
Min
7.5
1000
10
3
3
-
-
3
2
1
2
1
2
1
2
1
2
3
3
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
Max
Min
8
1000
10
3
3
-
-
3
2
1
2
1
2
1
2
1
2
3
3
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
Max
Min
10
1000
12
3
3
-
-
3
2
1
2
1
2
1
2
1
2
3
3
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
Max
Min
10
1000
ns
ns
ns
ns
2
CAS Latency = 2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
Max
ns
-K
-H
-8
-P
-S
Unit
Note
Clock high pulse width
Clock low pulse width
Access time from
clock
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
Command setup time
Command hold time
CLK to data output in low Z-time
CLK to data output
in high Z-time
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 1.3/Nov. 01
7