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HY57V561620HLT-H 参数 Datasheet PDF下载

HY57V561620HLT-H图片预览
型号: HY57V561620HLT-H
PDF下载: 下载PDF文件 查看货源
内容描述: X16 SDRAM\n [x16 SDRAM ]
分类和应用: 动态存储器
文件页数/大小: 13 页 / 174 K
品牌: ETC [ ETC ]
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HY57V561620H(L)T  
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)  
-6  
-K  
- H  
-8  
-P  
-S  
Parameter  
Symbol  
Unit  
Note  
Min  
6
Max  
Min  
7.5  
7.5  
2.5  
2.5  
-
Max  
Min  
7.5  
10  
2.5  
2.5  
-
Max  
Min  
8
Max  
Min  
10  
10  
3
Max  
Min  
10  
12  
3
Max  
CAS Latency = 3 tCK3  
CAS Latency = 2 tCK2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
System clock  
cycle time  
1000  
1000  
1000  
1000  
1000  
1000  
10  
2.5  
2.5  
-
10  
3
Clock high pulse width  
Clock low pulse width  
tCHW  
tCLW  
-
-
-
-
-
-
-
-
-
1
1
-
-
-
3
3
3
CAS Latency = 3 tAC3  
CAS Latency = 2 tAC2  
tOH  
5.4  
5.4  
5.4  
-
6
6
-
-
6
6
-
-
6
6
-
Access time from  
clock  
2
-
6
-
5.4  
-
6
-
-
-
Data-out hold time  
2.7  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
2
-
-
2.7  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1
-
2.7  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
2
-
-
3
3
3
Data-Input setup time  
Data-Input hold time  
Address setup time  
Address hold time  
tDS  
-
2
-
2
-
2
-
1
1
1
1
1
1
1
1
tDH  
-
-
-
1
-
1
-
1
-
tAS  
-
-
-
2
-
2
-
2
-
tAH  
-
-
-
1
-
1
-
1
-
CKE setup time  
tCKS  
tCKH  
tCS  
-
-
-
2
-
2
-
2
-
CKE hold time  
-
-
-
-
1
-
1
-
1
-
Command setup time  
Command hold time  
CLK to data output in low Z-time  
-
-
2
-
2
-
2
-
tCH  
-
-
-
1
-
1
-
1
-
tOLZ  
-
-
-
2
-
2
-
2
-
CAS Latency = 3 tOHZ3  
CAS Latency = 2 tOHZ2  
2.7  
3
5.4  
6
2.7  
2.7  
5.4  
5.4  
2.7  
3
5.4  
6
3
6
6
3
6
6
3
6
6
CLK to data output  
in high Z-time  
3
3
3
Note :  
1.Assume tR / tF (input rise and fall time ) is 1ns  
2.Access times to be measured with input signals of 1v/ns edge rate  
Rev. 1.3/Nov. 01  
7