HT1625
A.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max. Unit
VDD
3V
5V
3V
5V
3V
5V
3V
5V
22
24
¾
¾
44
48
¾
¾
¾
¾
¾
¾
¾
32
32
40
40
¾
kHz
kHz
kHz
kHz
Hz
fSYS1
System Clock
On-chip RC oscillator
External clock source
On-chip RC oscillator
32
fSYS2
System Clock
32
¾
64
80
80
¾
fLCD1
LCD Frame Frequency
64
Hz
64
Hz
fLCD2
tCOM
fCLK1
LCD Frame Frequency
LCD Common Period
External clock source
n: Number of COM
Duty cycle 50%
64
Hz
¾
n/fLCD
sec
kHz
kHz
kHz
kHz
¾
3V
5V
3V
5V
¾
150
300
75
150
¾
¾
¾
¾
Serial Data Clock (WR Pin)
fCLK2
Serial Data Clock (RD Pin)
Duty cycle 50%
CS
Serial Interface Reset Pulse Width
(Figure 3)
tCS
250
ns
¾
¾
¾
Write mode
Read mode
Write mode
Read mode
3.34
6.67
1.67
3.34
¾
¾
¾
¾
¾
¾
¾
¾
3V
ms
tCLK
WR, RD Input Pulse Width (Figure 1)
5V
ms
ns
ns
ns
ns
ns
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
Rise or Fall Time Serial Data Clock
Width (Figure 1)
tr, tf
120
120
120
100
100
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Setup Time for DATA to WR, RD
Clock Width (Figure 2)
tsu
th
Hold Time for DATA to WR, RD Clock
Width (Figure 2)
Setup Time for CS to WR, RD Clock
Width (Figure 3)
tsu1
Hold Time for CS to WR, RD Clock
Width (Figure 3)
th1
V
A
L
I
D
D
A
T
A
V
G
D
D
t
f
t
r
5
0
%
D
B
V
G
D
D
W
R
,
R
D
N
D
9
0
%
5
0
%
t
s
u
t
h
C
l
o
c
k
N
D
1
0
%
t
C
L
K
t
C L K
V
G
D
D
W
R
,
R
D
5
0
%
C
l
o
c
k
N
D
Figure 1
Figure 2
t
C S
V
G
D
D
C
S
5
0
%
N
D
t
h 1
t
s u 1
V
G
D
D
W
R
,
R
D
5
0
%
C
l
o
c
k
N
D
ꢀ
I
R
S
T
L
A
S
T
C
l
o
c
k
C
l
o
c
k
Figure 3
Rev. 1.10
7
September 11, 2002
ETC [ ETC ]
