MAX 3000A Programmable Logic Device Family Data Sheet
Table 20. EPM3256A Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
–7
Unit
–5
–10
Min
Max Min
Max
Min Max
tCLR
tPIA
Register clear time
PIA delay
1.6
1.7
4.0
2.3
2.4
4.0
3.0
3.2
5.0
ns
ns
ns
(2)
(5)
tLPA
Low–power adder
Table 21. EPM3512A External Timing Parameters
Note (1)
Symbol Parameter Conditions
Speed Grade
Unit
-7
-10
Min
Max
Min
Max
tPD1
Input to non-registered output C1 = 35 pF (2)
7.5
7.5
10.0
10.0
ns
ns
tPD2
I/O input to non-registered
output
C1 = 35 pF (2)
tSU
tH
Global clock setup time
Global clock hold time
(2)
(2)
5.6
0.0
3.0
7.6
0.0
3.0
ns
ns
ns
tFSU
Global clock setup time of fast
input
tFH
Global clock hold time of fast
input
0.0
0.0
ns
tCO1
tCH
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
C1 = 35 pF
1.0
3.0
3.0
2.5
0.2
1.0
3.0
3.0
3.0
4.7
7.8
1.0
4.0
4.0
3.5
0.3
1.0
4.0
4.0
4.0
6.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCL
tASU
tAH
(2)
(2)
tACO1
tACH
tACL
tCPPW
C1 = 35 pF (2)
10.4
Minimum pulse width for clear (3)
and preset
tCNT
fCNT
Minimum global clock period
(2)
8.6
8.6
11.5
11.5
ns
Maximum internal global clock (2), (4)
116.3
116.3
87.0
87.0
MHz
frequency
tACNT
fACNT
Minimum array clock period
(2)
ns
Maximum internal array clock (2), (4)
MHz
frequency
32
Altera Corporation
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