MAX 3000A Programmable Logic Device Family Data Sheet
Figure 7
shows the timing information for the JTAG signals.
Figure 7. MAX 3000A JTAG Waveforms
TMS
TDI
t
JCP
t
JCH
TCK
t
JPZX
TDO
t
JSSU
Signal
to Be
Captured
Signal
to Be
Driven
t
JSH
t
JPCO
t
JPXZ
t
JCL
t
JPSU
t
JPH
t
JSZX
t
JSCO
t
JSXZ
Table 7
shows the JTAG timing parameters and values for MAX 3000A
devices.
Table 7. JTAG Timing Parameters & Values for MAX 3000A Devices
Symbol
t
JCP
t
JCH
t
JCL
t
JPSU
t
JPH
t
JPCO
t
JPZX
t
JPXZ
t
JSSU
t
JSH
t
JSCO
t
JSZX
t
JSXZ
TCK
clock period
TCK
clock high time
TCK
clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
20
45
25
25
25
Parameter
Min
100
50
50
20
45
Max
Unit
ns
ns
ns
ns
ns
25
25
25
ns
ns
ns
ns
ns
ns
ns
ns
Altera Corporation
15
ETC [ ETC ]
